cpldfit:  version I.31                              Xilinx Inc.
                                  Fitter Report
Design Name: kiserlet_top                        Date:  5-19-2007,  9:17PM
Device Used: XC2C256-7-TQ144
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
69 /256 ( 27%) 137 /896  ( 15%) 119 /640  ( 19%) 65 /256 ( 25%) 14 /118 ( 12%)

** Function Block Resources **

Function Mcells   FB Inps  Pterms   IO       CTC      CTR      CTS      CTE     
Block    Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1      16/16*    15/40    15/56     0/ 6    1/1*     0/1      0/1      0/1
FB2      16/16*    34/40    32/56     0/ 8    1/1*     0/1      0/1      0/1
FB3      16/16*    18/40    34/56     0/ 6    1/1*     0/1      0/1      0/1
FB4       9/16     21/40    26/56     0/ 8    1/1*     0/1      0/1      0/1
FB5       5/16     11/40    13/56     5/ 5*   1/1*     0/1      0/1      0/1
FB6       4/16     11/40     7/56     3/ 8    1/1*     0/1      0/1      0/1
FB7       3/16      9/40    10/56     3/ 8    1/1*     0/1      0/1      0/1
FB8       0/16      0/40     0/56     0/ 8    0/1      0/1      0/1      0/1
FB9       0/16      0/40     0/56     0/ 8    0/1      0/1      0/1      0/1
FB10      0/16      0/40     0/56     0/ 9    0/1      0/1      0/1      0/1
FB11      0/16      0/40     0/56     0/ 8    0/1      0/1      0/1      0/1
FB12      0/16      0/40     0/56     0/ 6    0/1      0/1      0/1      0/1
FB13      0/16      0/40     0/56     0/ 8    0/1      0/1      0/1      0/1
FB14      0/16      0/40     0/56     0/ 8    0/1      0/1      0/1      0/1
FB15      0/16      0/40     0/56     0/ 7    0/1      0/1      0/1      0/1
FB16      0/16      0/40     0/56     0/ 7    0/1      0/1      0/1      0/1
         -----    -------  -------   -----    ---      ---      ---      ---
Total    69/256   119/640  137/896   11/118   7/16     0/16     0/16     0/16

CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable

* - Resource is exhausted

** Global Control Resources **

GCK         GSR         GTS         
Used/Tot    Used/Tot    Used/Tot    
1/3         0/1         0/4

Signal 'CLK' mapped onto global clock net GCK2.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    2           2    |  I/O              :     8    108
Output        :   11          11    |  GCK/IO           :     3      3
Bidirectional :    0           0    |  GTS/IO           :     0      4
GCK           :    1           1    |  GSR/IO           :     1      1
GTS           :    0           0    |  CDR/IO           :     1      1
GSR           :    0           0    |  DGE/IO           :     1      1
                 ----        ----
        Total     14          14

End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld:823 - Clock CLK appearing in an OFFSET timespec currently must be
   explicitly declared as a global clock input (BUFG) in your design. The OFFSET
   constraint referring to this clock will be ignored.
WARNING:Cpld:823 - Clock CLK appearing in an OFFSET timespec currently must be
   explicitly declared as a global clock input (BUFG) in your design. The OFFSET
   constraint referring to this clock will be ignored.
WARNING:Cpld:823 - Clock CLK appearing in an OFFSET timespec currently must be
   explicitly declared as a global clock input (BUFG) in your design. The OFFSET
   constraint referring to this clock will be ignored.
WARNING:Cpld:823 - Clock CLK appearing in an OFFSET timespec currently must be
   explicitly declared as a global clock input (BUFG) in your design. The OFFSET
   constraint referring to this clock will be ignored.
WARNING:Cpld:823 - Clock CLK appearing in an OFFSET timespec currently must be
   explicitly declared as a global clock input (BUFG) in your design. The OFFSET
   constraint referring to this clock will be ignored.
WARNING:Cpld:823 - Clock CLK appearing in an OFFSET timespec currently must be
   explicitly declared as a global clock input (BUFG) in your design. The OFFSET
   constraint referring to this clock will be ignored.
WARNING:Cpld:823 - Clock CLK appearing in an OFFSET timespec currently must be
   explicitly declared as a global clock input (BUFG) in your design. The OFFSET
   constraint referring to this clock will be ignored.
WARNING:Cpld:823 - Clock CLK appearing in an OFFSET timespec currently must be
   explicitly declared as a global clock input (BUFG) in your design. The OFFSET
   constraint referring to this clock will be ignored.
*************************  Summary of Mapped Logic  ************************

** 11 Outputs **

Signal              Total Total Loc     Pin   Pin       Pin     I/O      I/O       Slew Reg     Reg Init
Name                Pts   Inps          No.   Type      Use     STD      Style     Rate Use     State
EN1                 0     0     FB5_2   33    I/O       O       LVCMOS33           FAST         
OUT<1>              4     5     FB5_4   32    GCK/I/O   O       LVCMOS33           FAST DFF     RESET
OUT<2>              4     6     FB5_5   31    I/O       O       LVCMOS33           FAST DFF     RESET
OUT<3>              4     7     FB5_6   30    GCK/I/O   O       LVCMOS33           FAST DFF     RESET
OUT<4>              4     8     FB5_14  28    I/O       O       LVCMOS33           FAST DFF     RESET
DIR1                0     0     FB6_1   34    I/O       O       LVCMOS33           FAST         
OUT<0>              3     3     FB6_2   35    CDR/I/O   O       LVCMOS33           FAST DEFF    RESET
SEND                4     7     FB6_12  39    DGE/I/O   O       LVCMOS33           FAST TFF     RESET
OUT<5>              4     5     FB7_5   26    I/O       O       LVCMOS33           FAST DFF     RESET
OUT<6>              4     6     FB7_6   25    I/O       O       LVCMOS33           FAST DFF     RESET
OUT<7>              4     7     FB7_11  24    I/O       O       LVCMOS33           FAST DFF     RESET

** 58 Buried Nodes **

Signal              Total Total Loc     Reg     Reg Init
Name                Pts   Inps          Use     State
postsc<3>           2     4     FB1_1   TFF     RESET
postsc<2>           2     3     FB1_2   TFF     RESET
postsc<9>           2     10    FB1_3   TFF     RESET
postsc<8>           2     9     FB1_4   TFF     RESET
postsc<1>           2     2     FB1_5   TFF     RESET
postsc<7>           2     8     FB1_6   TFF     RESET
postsc<0>           1     1     FB1_7   TFF     RESET
orajel              1     5     FB1_8   DFF     RESET
p1/prescale<4>      1     4     FB1_9   TFF     RESET
p1/prescale<3>      1     3     FB1_10  TFF     RESET
p1/prescale<2>      1     2     FB1_11  TFF     RESET
postsc<6>           2     7     FB1_12  TFF     RESET
postsc<5>           2     6     FB1_13  TFF     RESET
postsc<4>           2     5     FB1_14  TFF     RESET
p1/prescale<1>      1     1     FB1_15  TFF     RESET
p1/prescale<0>      0     0     FB1_16  TFF     RESET
t1/shdata<6>        5     8     FB2_1   TFF     RESET
t1/bitsz<0>         3     6     FB2_2   TFF     RESET
t1/shdata<7>        5     8     FB2_3   TFF     RESET
t1/shdata<8>        5     8     FB2_4   TFF     RESET
t1/shdata<9>        4     7     FB2_5   DFF     RESET
postsc<10>          2     11    FB2_6   TFF     RESET
postsc<11>          2     12    FB2_7   TFF     RESET
postsc<12>          2     13    FB2_8   TFF     RESET
postsc<13>          2     14    FB2_9   TFF     RESET
postsc<14>          2     15    FB2_10  TFF     RESET
postsc<15>          2     16    FB2_11  TFF     RESET
N_PZ_504            2     8     FB2_12          
t1/bitsz<3>         3     9     FB2_13  TFF     RESET
t1/bitsz<2>         3     8     FB2_14  TFF     RESET
t1/bitsz<1>         3     7     FB2_15  TFF     RESET
trmt                2     19    FB2_16  DFF     RESET
bus1<7>             3     5     FB3_1   DEFF    RESET
bus1<6>             3     5     FB3_2   DEFF    RESET
bus1<5>             3     5     FB3_3   DEFF    RESET
bus1<2>             3     5     FB3_4   DEFF    RESET
bus1<4>             3     5     FB3_5   DEFF    RESET
bus1<1>             3     5     FB3_6   DEFF    RESET
bus1<0>             3     5     FB3_7   DEFF    RESET
r1/csample<1>       2     4     FB3_8   DFF     RESET

Signal              Total Total Loc     Reg     Reg Init
Name                Pts   Inps          Use     State
r1/csample<0>       2     4     FB3_9   DFF     RESET
r1/cbit<2>          3     7     FB3_10  TFF     RESET
r1/cbit<0>          5     8     FB3_11  TFF     RESET
r1/cbit<3>          4     8     FB3_12  TFF     RESET
r1/cbit<1>          4     8     FB3_13  TFF     RESET
N_PZ_372            1     5     FB3_14          
r1/startb           3     9     FB3_15  DFF     RESET
bus1<3>             3     5     FB3_16  DEFF    RESET
tr_inproc           3     3     FB4_7   DEFF    RESET
t1/div<1>           2     4     FB4_8   DFF     RESET
t1/div<0>           2     4     FB4_9   DFF     RESET
t1/shdata<5>        5     8     FB4_10  TFF     RESET
t1/shdata<4>        5     8     FB4_11  TFF     RESET
t1/shdata<3>        5     8     FB4_13  TFF     RESET
r1/data<8>          3     6     FB4_14  TFF     RESET
t1/shdata<1>        4     7     FB4_15  TFF     RESET
t1/shdata<2>        5     8     FB4_16  TFF     RESET
r1/data<9>          2     4     FB6_15  DEFF    RESET

** 3 Inputs **

Signal              Loc     Pin   Pin       Pin     I/O      I/O
Name                        No.   Type      Use     STD      Style
BUTTON              FB1_3   143   GSR/I/O   I       LVCMOS33 KPR
CLK                 FB6_4   38    GCK/I/O   GCK     LVCMOS33 KPR
REC                 FB6_15  42    I/O       I       LVCMOS33 KPR

Legend:
Pin No.   - ~     - User Assigned
I/O Style - OD    - OpenDrain
          - PU    - Pullup
          - KPR   - Keeper
          - S     - SchmittTrigger
          - DG    - DataGate
Reg Use   - LATCH - Transparent latch
          - DFF   - D-flip-flop
          - DEFF  - D-flip-flop with clock enable
          - TFF   - T-flip-flop
          - TDFF  - Dual-edge-triggered T-flip-flop
          - DDFF  - Dual-edge-triggered flip-flop
          - DDEFF - Dual-edge-triggered flip-flop with clock enable
          /S (after any above flop/latch type) indicates initial state is Set
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
              VRF - Vref
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               15/25
Number of function block control terms used/remaining:        1/3
Number of PLA product terms used/remaining:                   15/41
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
postsc<3>                     2     FB1_1        (b)     (b)    +          
postsc<2>                     2     FB1_2        (b)     (b)    +          
postsc<9>                     2     FB1_3   143  GSR/I/O I      +          
postsc<8>                     2     FB1_4   142  I/O     (b)    +          
postsc<1>                     2     FB1_5        (b)     (b)    +          
postsc<7>                     2     FB1_6   140  I/O     (b)    +          
postsc<0>                     1     FB1_7        (b)     (b)    +          
orajel                        1     FB1_8        (b)     (b)               
p1/prescale<4>                1     FB1_9        (b)     (b)               
p1/prescale<3>                1     FB1_10       (b)     (b)               
p1/prescale<2>                1     FB1_11       (b)     (b)               
postsc<6>                     2     FB1_12  139  I/O     (b)    +          
postsc<5>                     2     FB1_13  138  I/O     (b)    +          
postsc<4>                     2     FB1_14  137  I/O     (b)    +          
p1/prescale<1>                1     FB1_15       (b)     (b)               
p1/prescale<0>                0     FB1_16       (b)     (b)               

Signals Used by Logic in Function Block
  1: orajel             6: p1/prescale<4>    11: postsc<4> 
  2: p1/prescale<0>     7: postsc<0>         12: postsc<5> 
  3: p1/prescale<1>     8: postsc<1>         13: postsc<6> 
  4: p1/prescale<2>     9: postsc<2>         14: postsc<7> 
  5: p1/prescale<3>    10: postsc<3>         15: postsc<8> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
postsc<3>         X.....XXX............................... 4       
postsc<2>         X.....XX................................ 3       
postsc<9>         X.....XXXXXXXXX......................... 10      
postsc<8>         X.....XXXXXXXX.......................... 9       
postsc<1>         X.....X................................. 2       
postsc<7>         X.....XXXXXXX........................... 8       
postsc<0>         X....................................... 1       
orajel            .XXXXX.................................. 5       
p1/prescale<4>    .XXXX................................... 4       
p1/prescale<3>    .XXX.................................... 3       
p1/prescale<2>    .XX..................................... 2       
postsc<6>         X.....XXXXXX............................ 7       
postsc<5>         X.....XXXXX............................. 6       
postsc<4>         X.....XXXX.............................. 5       
p1/prescale<1>    .X...................................... 1       
p1/prescale<0>    ........................................ 0       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB2  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               34/6
Number of function block control terms used/remaining:        1/3
Number of PLA product terms used/remaining:                   32/24
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
t1/shdata<6>                  5     FB2_1   2    GTS/I/O (b)    +          
t1/bitsz<0>                   3     FB2_2        (b)     (b)    +          
t1/shdata<7>                  5     FB2_3   3    GTS/I/O (b)    +          
t1/shdata<8>                  5     FB2_4   4    I/O     (b)    +          
t1/shdata<9>                  4     FB2_5   5    GTS/I/O (b)    +          
postsc<10>                    2     FB2_6        (b)     (b)    +          
postsc<11>                    2     FB2_7        (b)     (b)    +          
postsc<12>                    2     FB2_8        (b)     (b)    +          
postsc<13>                    2     FB2_9        (b)     (b)    +          
postsc<14>                    2     FB2_10       (b)     (b)    +          
postsc<15>                    2     FB2_11       (b)     (b)    +          
N_PZ_504                      2     FB2_12  6    GTS/I/O (b)               
t1/bitsz<3>                   3     FB2_13  7    I/O     (b)    +          
t1/bitsz<2>                   3     FB2_14  9    I/O     (b)    +          
t1/bitsz<1>                   3     FB2_15  10   I/O     (b)    +          
trmt                          2     FB2_16       (b)     (b)    +          

Signals Used by Logic in Function Block
  1: BUTTON            13: postsc<15>        24: t1/bitsz<1> 
  2: OUT<4>            14: postsc<1>         25: t1/bitsz<2> 
  3: OUT<5>            15: postsc<2>         26: t1/bitsz<3> 
  4: OUT<6>            16: postsc<3>         27: t1/div<0> 
  5: OUT<7>            17: postsc<4>         28: t1/div<1> 
  6: orajel            18: postsc<5>         29: t1/shdata<6> 
  7: postsc<0>         19: postsc<6>         30: t1/shdata<7> 
  8: postsc<10>        20: postsc<7>         31: t1/shdata<8> 
  9: postsc<11>        21: postsc<8>         32: t1/shdata<9> 
 10: postsc<12>        22: postsc<9>         33: tr_inproc 
 11: postsc<13>        23: t1/bitsz<0>       34: trmt 
 12: postsc<14>       

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
t1/shdata<6>      .X...X....................XXXX..XX...... 8       
t1/bitsz<0>       .....X................X...XX....XX...... 6       
t1/shdata<7>      ..X..X....................XX.XX.XX...... 8       
t1/shdata<8>      ...X.X....................XX..XXXX...... 8       
t1/shdata<9>      ....XX....................XX...XXX...... 7       
postsc<10>        .....XX......XXXXXXXXX.................. 11      
postsc<11>        .....XXX.....XXXXXXXXX.................. 12      
postsc<12>        .....XXXX....XXXXXXXXX.................. 13      
postsc<13>        .....XXXXX...XXXXXXXXX.................. 14      
postsc<14>        .....XXXXXX..XXXXXXXXX.................. 15      
postsc<15>        .....XXXXXXX.XXXXXXXXX.................. 16      
N_PZ_504          ......................XXXXXX....XX...... 8       
t1/bitsz<3>       .....X................XXXXXX....XX...... 9       
t1/bitsz<2>       .....X................XXX.XX....XX...... 8       
t1/bitsz<1>       .....X................XX..XX....XX...... 7       
trmt              X....XXXXXXXXXXXXXXXXX..........X....... 19      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB3  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               18/22
Number of function block control terms used/remaining:        1/3
Number of PLA product terms used/remaining:                   34/22
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
bus1<7>                       3     FB3_1   136  I/O     (b)    +          
bus1<6>                       3     FB3_2   135  I/O     (b)    +          
bus1<5>                       3     FB3_3   134  I/O     (b)    +          
bus1<2>                       3     FB3_4        (b)     (b)    +          
bus1<4>                       3     FB3_5   133  I/O     (b)    +          
bus1<1>                       3     FB3_6        (b)     (b)    +          
bus1<0>                       3     FB3_7        (b)     (b)    +          
r1/csample<1>                 2     FB3_8        (b)     (b)    +          
r1/csample<0>                 2     FB3_9        (b)     (b)    +          
r1/cbit<2>                    3     FB3_10       (b)     (b)    +          
r1/cbit<0>                    5     FB3_11       (b)     (b)    +          
r1/cbit<3>                    4     FB3_12       (b)     (b)    +          
r1/cbit<1>                    4     FB3_13       (b)     (b)    +          
N_PZ_372                      1     FB3_14  132  I/O     (b)               
r1/startb                     3     FB3_15       (b)     (b)    +          
bus1<3>                       3     FB3_16  131  I/O     (b)    +          

Signals Used by Logic in Function Block
  1: REC                7: bus1<5>           13: r1/cbit<2> 
  2: bus1<0>            8: bus1<6>           14: r1/cbit<3> 
  3: bus1<1>            9: bus1<7>           15: r1/csample<0> 
  4: bus1<2>           10: orajel            16: r1/csample<1> 
  5: bus1<3>           11: r1/cbit<0>        17: r1/data<8> 
  6: bus1<4>           12: r1/cbit<1>        18: r1/startb 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
bus1<7>           .........X....XXXX...................... 5       
bus1<6>           ........XX....XX.X...................... 5       
bus1<5>           .......X.X....XX.X...................... 5       
bus1<2>           ....X....X....XX.X...................... 5       
bus1<4>           ......X..X....XX.X...................... 5       
bus1<1>           ...X.....X....XX.X...................... 5       
bus1<0>           ..X......X....XX.X...................... 5       
r1/csample<1>     .........X....XX.X...................... 4       
r1/csample<0>     .........X....XX.X...................... 4       
r1/cbit<2>        .........XXXX.XX.X...................... 7       
r1/cbit<0>        .........XXXXXXX.X...................... 8       
r1/cbit<3>        .........XXXXXXX.X...................... 8       
r1/cbit<1>        .........XXXXXXX.X...................... 8       
N_PZ_372          .XXXXX.................................. 5       
r1/startb         X........XXXXXXX.X...................... 9       
bus1<3>           .....X...X....XX.X...................... 5       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB4  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               21/19
Number of function block control terms used/remaining:        1/3
Number of PLA product terms used/remaining:                   26/30
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB4_1   11   I/O           
(unused)                      0     FB4_2   12   I/O           
(unused)                      0     FB4_3   13   I/O           
(unused)                      0     FB4_4   14   I/O           
(unused)                      0     FB4_5   15   I/O           
(unused)                      0     FB4_6   16   I/O           
tr_inproc                     3     FB4_7        (b)     (b)    +          
t1/div<1>                     2     FB4_8        (b)     (b)    +          
t1/div<0>                     2     FB4_9        (b)     (b)    +          
t1/shdata<5>                  5     FB4_10       (b)     (b)    +          
t1/shdata<4>                  5     FB4_11       (b)     (b)    +          
(unused)                      0     FB4_12  17   I/O           
t1/shdata<3>                  5     FB4_13       (b)     (b)    +          
r1/data<8>                    3     FB4_14  18   I/O     (b)    +          
t1/shdata<1>                  4     FB4_15       (b)     (b)    +          
t1/shdata<2>                  5     FB4_16       (b)     (b)    +          

Signals Used by Logic in Function Block
  1: N_PZ_504           8: r1/csample<1>     15: t1/shdata<2> 
  2: OUT<0>             9: r1/data<8>        16: t1/shdata<3> 
  3: OUT<1>            10: r1/data<9>        17: t1/shdata<4> 
  4: OUT<2>            11: r1/startb         18: t1/shdata<5> 
  5: OUT<3>            12: t1/div<0>         19: t1/shdata<6> 
  6: orajel            13: t1/div<1>         20: tr_inproc 
  7: r1/csample<0>     14: t1/shdata<1>      21: trmt 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
tr_inproc         X....X..............X................... 3       
t1/div<1>         .....X.....XX.......X................... 4       
t1/div<0>         .....X.....XX.......X................... 4       
t1/shdata<5>      ....XX.....XX....XXXX................... 8       
t1/shdata<4>      ...X.X.....XX...XX.XX................... 8       
t1/shdata<3>      ..X..X.....XX..XX..XX................... 8       
r1/data<8>        .....XXXXXX............................. 6       
t1/shdata<1>      .....X.....XXXX....XX................... 7       
t1/shdata<2>      .X...X.....XX.XX...XX................... 8       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB5  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               11/29
Number of function block control terms used/remaining:        1/3
Number of PLA product terms used/remaining:                   13/43
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB5_1        (b)           
EN1                           0     FB5_2   33   I/O     O                 
(unused)                      0     FB5_3        (b)           
OUT<1>                        4     FB5_4   32   GCK/I/O O      +          
OUT<2>                        4     FB5_5   31   I/O     O      +          
OUT<3>                        4     FB5_6   30   GCK/I/O O      +          
(unused)                      0     FB5_7        (b)           
(unused)                      0     FB5_8        (b)           
(unused)                      0     FB5_9        (b)           
(unused)                      0     FB5_10       (b)           
(unused)                      0     FB5_11       (b)           
(unused)                      0     FB5_12       (b)           
(unused)                      0     FB5_13       (b)           
OUT<4>                        4     FB5_14  28   I/O     O      +          
(unused)                      0     FB5_15       (b)           
(unused)                      0     FB5_16       (b)           

Signals Used by Logic in Function Block
  1: OUT<1>             5: bus1<0>            9: bus1<4> 
  2: OUT<2>             6: bus1<1>           10: orajel 
  3: OUT<3>             7: bus1<2>           11: r1/startb 
  4: OUT<4>             8: bus1<3>          

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
EN1               ........................................ 0       
OUT<1>            X...XX...XX............................. 5       
OUT<2>            .X..XXX..XX............................. 6       
OUT<3>            ..X.XXXX.XX............................. 7       
OUT<4>            ...XXXXXXXX............................. 8       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB6  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               11/29
Number of function block control terms used/remaining:        1/3
Number of PLA product terms used/remaining:                   7/49
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
DIR1                          0     FB6_1   34   I/O     O                 
OUT<0>                        3     FB6_2   35   CDR/I/O O      +          
(unused)                      0     FB6_3        (b)           
(unused)                      0     FB6_4   38   GCK/I/O GCK   
(unused)                      0     FB6_5        (b)           
(unused)                      0     FB6_6        (b)           
(unused)                      0     FB6_7        (b)           
(unused)                      0     FB6_8        (b)           
(unused)                      0     FB6_9        (b)           
(unused)                      0     FB6_10       (b)           
(unused)                      0     FB6_11       (b)           
SEND                          4     FB6_12  39   DGE/I/O O      +          
(unused)                      0     FB6_13  40   I/O           
(unused)                      0     FB6_14  41   I/O           
r1/data<9>                    2     FB6_15  42   I/O     I      +          
(unused)                      0     FB6_16  43   I/O           

Signals Used by Logic in Function Block
  1: SEND               5: r1/csample<1>      9: t1/shdata<1> 
  2: bus1<0>            6: r1/startb         10: tr_inproc 
  3: orajel             7: t1/div<0>         11: trmt 
  4: r1/csample<0>      8: t1/div<1>        

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
DIR1              ........................................ 0       
OUT<0>            .XX..X.................................. 3       
SEND              X.X...XXXXX............................. 7       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB7  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               9/31
Number of function block control terms used/remaining:        1/3
Number of PLA product terms used/remaining:                   10/46
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB7_1        (b)           
(unused)                      0     FB7_2        (b)           
(unused)                      0     FB7_3        (b)           
(unused)                      0     FB7_4        (b)           
OUT<5>                        4     FB7_5   26   I/O     O      +          
OUT<6>                        4     FB7_6   25   I/O     O      +          
(unused)                      0     FB7_7        (b)           
(unused)                      0     FB7_8        (b)           
(unused)                      0     FB7_9        (b)           
(unused)                      0     FB7_10       (b)           
OUT<7>                        4     FB7_11  24   I/O     O      +          
(unused)                      0     FB7_12  23   I/O           
(unused)                      0     FB7_13  22   I/O           
(unused)                      0     FB7_14  21   I/O           
(unused)                      0     FB7_15  20   I/O           
(unused)                      0     FB7_16  19   I/O           

Signals Used by Logic in Function Block
  1: N_PZ_372           4: OUT<7>             7: bus1<7> 
  2: OUT<5>             5: bus1<5>            8: orajel 
  3: OUT<6>             6: bus1<6>            9: r1/startb 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
OUT<5>            XX..X..XX............................... 5       
OUT<6>            X.X.XX.XX............................... 6       
OUT<7>            X..XXXXXX............................... 7       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB8  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB8_1   44   I/O           
(unused)                      0     FB8_2   45   I/O           
(unused)                      0     FB8_3   46   I/O           
(unused)                      0     FB8_4        (b)           
(unused)                      0     FB8_5   48   I/O           
(unused)                      0     FB8_6   49   I/O           
(unused)                      0     FB8_7        (b)           
(unused)                      0     FB8_8        (b)           
(unused)                      0     FB8_9        (b)           
(unused)                      0     FB8_10       (b)           
(unused)                      0     FB8_11  50   I/O           
(unused)                      0     FB8_12  51   I/O           
(unused)                      0     FB8_13  52   I/O           
(unused)                      0     FB8_14       (b)           
(unused)                      0     FB8_15       (b)           
(unused)                      0     FB8_16       (b)           
*********************************** FB9  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB9_1   112  I/O           
(unused)                      0     FB9_2   113  I/O           
(unused)                      0     FB9_3        (b)           
(unused)                      0     FB9_4   114  I/O           
(unused)                      0     FB9_5        (b)           
(unused)                      0     FB9_6   115  I/O           
(unused)                      0     FB9_7        (b)           
(unused)                      0     FB9_8        (b)           
(unused)                      0     FB9_9        (b)           
(unused)                      0     FB9_10       (b)           
(unused)                      0     FB9_11       (b)           
(unused)                      0     FB9_12  116  I/O           
(unused)                      0     FB9_13  117  I/O           
(unused)                      0     FB9_14  118  I/O           
(unused)                      0     FB9_15  119  I/O           
(unused)                      0     FB9_16       (b)           
*********************************** FB10 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB10_1  111  I/O           
(unused)                      0     FB10_2  110  I/O           
(unused)                      0     FB10_3  107  I/O           
(unused)                      0     FB10_4  106  I/O           
(unused)                      0     FB10_5  105  I/O           
(unused)                      0     FB10_6  104  I/O           
(unused)                      0     FB10_7       (b)           
(unused)                      0     FB10_8       (b)           
(unused)                      0     FB10_9       (b)           
(unused)                      0     FB10_10      (b)           
(unused)                      0     FB10_11      (b)           
(unused)                      0     FB10_12 103  I/O           
(unused)                      0     FB10_13      (b)           
(unused)                      0     FB10_14 102  I/O           
(unused)                      0     FB10_15      (b)           
(unused)                      0     FB10_16 101  I/O           
*********************************** FB11 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB11_1       (b)           
(unused)                      0     FB11_2       (b)           
(unused)                      0     FB11_3       (b)           
(unused)                      0     FB11_4       (b)           
(unused)                      0     FB11_5  120  I/O           
(unused)                      0     FB11_6  121  I/O           
(unused)                      0     FB11_7       (b)           
(unused)                      0     FB11_8       (b)           
(unused)                      0     FB11_9       (b)           
(unused)                      0     FB11_10      (b)           
(unused)                      0     FB11_11 124  I/O           
(unused)                      0     FB11_12 125  I/O           
(unused)                      0     FB11_13 126  I/O           
(unused)                      0     FB11_14 128  I/O           
(unused)                      0     FB11_15 129  I/O           
(unused)                      0     FB11_16 130  I/O           
*********************************** FB12 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB12_1       (b)           
(unused)                      0     FB12_2  100  I/O           
(unused)                      0     FB12_3       (b)           
(unused)                      0     FB12_4       (b)           
(unused)                      0     FB12_5       (b)           
(unused)                      0     FB12_6       (b)           
(unused)                      0     FB12_7       (b)           
(unused)                      0     FB12_8       (b)           
(unused)                      0     FB12_9       (b)           
(unused)                      0     FB12_10      (b)           
(unused)                      0     FB12_11 98   I/O           
(unused)                      0     FB12_12 97   I/O           
(unused)                      0     FB12_13 96   I/O           
(unused)                      0     FB12_14 95   I/O           
(unused)                      0     FB12_15 94   I/O           
(unused)                      0     FB12_16      (b)           
*********************************** FB13 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB13_1  75   I/O           
(unused)                      0     FB13_2  76   I/O           
(unused)                      0     FB13_3  77   I/O           
(unused)                      0     FB13_4       (b)           
(unused)                      0     FB13_5  78   I/O           
(unused)                      0     FB13_6  79   I/O           
(unused)                      0     FB13_7       (b)           
(unused)                      0     FB13_8       (b)           
(unused)                      0     FB13_9       (b)           
(unused)                      0     FB13_10      (b)           
(unused)                      0     FB13_11      (b)           
(unused)                      0     FB13_12 80   I/O           
(unused)                      0     FB13_13 81   I/O           
(unused)                      0     FB13_14 82   I/O           
(unused)                      0     FB13_15      (b)           
(unused)                      0     FB13_16      (b)           
*********************************** FB14 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB14_1  74   I/O           
(unused)                      0     FB14_2  71   I/O           
(unused)                      0     FB14_3  70   I/O           
(unused)                      0     FB14_4  69   I/O           
(unused)                      0     FB14_5       (b)           
(unused)                      0     FB14_6  68   I/O           
(unused)                      0     FB14_7       (b)           
(unused)                      0     FB14_8       (b)           
(unused)                      0     FB14_9       (b)           
(unused)                      0     FB14_10      (b)           
(unused)                      0     FB14_11      (b)           
(unused)                      0     FB14_12      (b)           
(unused)                      0     FB14_13 66   I/O           
(unused)                      0     FB14_14 64   I/O           
(unused)                      0     FB14_15      (b)           
(unused)                      0     FB14_16 61   I/O           
*********************************** FB15 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB15_1       (b)           
(unused)                      0     FB15_2  83   I/O           
(unused)                      0     FB15_3       (b)           
(unused)                      0     FB15_4       (b)           
(unused)                      0     FB15_5       (b)           
(unused)                      0     FB15_6       (b)           
(unused)                      0     FB15_7       (b)           
(unused)                      0     FB15_8       (b)           
(unused)                      0     FB15_9       (b)           
(unused)                      0     FB15_10      (b)           
(unused)                      0     FB15_11 85   I/O           
(unused)                      0     FB15_12 86   I/O           
(unused)                      0     FB15_13 87   I/O           
(unused)                      0     FB15_14 88   I/O           
(unused)                      0     FB15_15 91   I/O           
(unused)                      0     FB15_16 92   I/O           
*********************************** FB16 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB16_1       (b)           
(unused)                      0     FB16_2       (b)           
(unused)                      0     FB16_3       (b)           
(unused)                      0     FB16_4       (b)           
(unused)                      0     FB16_5  60   I/O           
(unused)                      0     FB16_6  59   I/O           
(unused)                      0     FB16_7       (b)           
(unused)                      0     FB16_8       (b)           
(unused)                      0     FB16_9       (b)           
(unused)                      0     FB16_10      (b)           
(unused)                      0     FB16_11 58   I/O           
(unused)                      0     FB16_12 57   I/O           
(unused)                      0     FB16_13 56   I/O           
(unused)                      0     FB16_14      (b)           
(unused)                      0     FB16_15 54   I/O           
(unused)                      0     FB16_16 53   I/O           
*******************************  Equations  ********************************

********** Mapped Logic **********


DIR1 <= NOT ('0');


EN1 <= '0';


N_PZ_372 <= (bus1(0) AND bus1(1) AND bus1(2) AND bus1(3) AND 
	bus1(4));


N_PZ_504 <= ((trmt)
	OR (tr_inproc AND NOT t1/bitsz(0) AND NOT t1/div(0) AND t1/div(1) AND 
	t1/bitsz(1) AND NOT t1/bitsz(2) AND t1/bitsz(3)));

FDCPE_OUT0: FDCPE port map (OUT(0),NOT bus1(0),orajel,'0','0',NOT r1/startb);

FDCPE_OUT1: FDCPE port map (OUT(1),OUT_D(1),orajel,'0','0','1');
OUT_D(1) <= ((r1/startb AND OUT(1))
	OR (bus1(0) AND NOT bus1(1) AND NOT r1/startb)
	OR (NOT bus1(0) AND bus1(1) AND NOT r1/startb));

FDCPE_OUT2: FDCPE port map (OUT(2),OUT_D(2),orajel,'0','0','1');
OUT_D(2) <= (bus1(2) AND NOT r1/startb)
	XOR ((r1/startb AND OUT(2))
	OR (bus1(0) AND bus1(1) AND NOT r1/startb));

FDCPE_OUT3: FDCPE port map (OUT(3),OUT_D(3),orajel,'0','0','1');
OUT_D(3) <= (bus1(3) AND NOT r1/startb)
	XOR ((r1/startb AND OUT(3))
	OR (bus1(0) AND bus1(1) AND bus1(2) AND NOT r1/startb));

FDCPE_OUT4: FDCPE port map (OUT(4),OUT_D(4),orajel,'0','0','1');
OUT_D(4) <= (bus1(4) AND NOT r1/startb)
	XOR ((r1/startb AND OUT(4))
	OR (bus1(0) AND bus1(1) AND bus1(2) AND bus1(3) AND 
	NOT r1/startb));

FDCPE_OUT5: FDCPE port map (OUT(5),OUT_D(5),orajel,'0','0','1');
OUT_D(5) <= ((r1/startb AND OUT(5))
	OR (bus1(5) AND NOT r1/startb AND NOT N_PZ_372)
	OR (NOT bus1(5) AND NOT r1/startb AND N_PZ_372));

FDCPE_OUT6: FDCPE port map (OUT(6),OUT_D(6),orajel,'0','0','1');
OUT_D(6) <= (bus1(6) AND NOT r1/startb)
	XOR ((r1/startb AND OUT(6))
	OR (bus1(5) AND NOT r1/startb AND N_PZ_372));

FDCPE_OUT7: FDCPE port map (OUT(7),OUT_D(7),orajel,'0','0','1');
OUT_D(7) <= (bus1(7) AND NOT r1/startb)
	XOR ((r1/startb AND OUT(7))
	OR (bus1(5) AND bus1(6) AND NOT r1/startb AND N_PZ_372));

FTCPE_SEND: FTCPE port map (SEND,SEND_T,orajel,'0','0','1');
SEND_T <= ((NOT tr_inproc AND NOT trmt AND NOT SEND)
	OR (NOT trmt AND NOT t1/div(0) AND t1/div(1) AND t1/shdata(1) AND 
	NOT SEND)
	OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND 
	NOT t1/shdata(1) AND SEND));

FDCPE_bus10: FDCPE port map (bus1(0),bus1(1),orajel,'0','0',bus1_CE(0));
bus1_CE(0) <= (r1/startb AND NOT r1/csample(0) AND r1/csample(1));

FDCPE_bus11: FDCPE port map (bus1(1),bus1(2),orajel,'0','0',bus1_CE(1));
bus1_CE(1) <= (r1/startb AND NOT r1/csample(0) AND r1/csample(1));

FDCPE_bus12: FDCPE port map (bus1(2),bus1(3),orajel,'0','0',bus1_CE(2));
bus1_CE(2) <= (r1/startb AND NOT r1/csample(0) AND r1/csample(1));

FDCPE_bus13: FDCPE port map (bus1(3),bus1(4),orajel,'0','0',bus1_CE(3));
bus1_CE(3) <= (r1/startb AND NOT r1/csample(0) AND r1/csample(1));

FDCPE_bus14: FDCPE port map (bus1(4),bus1(5),orajel,'0','0',bus1_CE(4));
bus1_CE(4) <= (r1/startb AND NOT r1/csample(0) AND r1/csample(1));

FDCPE_bus15: FDCPE port map (bus1(5),bus1(6),orajel,'0','0',bus1_CE(5));
bus1_CE(5) <= (r1/startb AND NOT r1/csample(0) AND r1/csample(1));

FDCPE_bus16: FDCPE port map (bus1(6),bus1(7),orajel,'0','0',bus1_CE(6));
bus1_CE(6) <= (r1/startb AND NOT r1/csample(0) AND r1/csample(1));

FDCPE_bus17: FDCPE port map (bus1(7),r1/data(8),orajel,'0','0',bus1_CE(7));
bus1_CE(7) <= (r1/startb AND NOT r1/csample(0) AND r1/csample(1));

FDCPE_orajel: FDCPE port map (orajel,orajel_D,CLK,'0','0','1');
orajel_D <= (p1/prescale(0) AND p1/prescale(1) AND p1/prescale(2) AND 
	p1/prescale(3) AND p1/prescale(4));

FTCPE_p1/prescale0: FTCPE port map (p1/prescale(0),'0',CLK,'0','0','1');

FTCPE_p1/prescale1: FTCPE port map (p1/prescale(1),p1/prescale(0),CLK,'0','0','1');

FTCPE_p1/prescale2: FTCPE port map (p1/prescale(2),p1/prescale_T(2),CLK,'0','0','1');
p1/prescale_T(2) <= (p1/prescale(0) AND p1/prescale(1));

FTCPE_p1/prescale3: FTCPE port map (p1/prescale(3),p1/prescale_T(3),CLK,'0','0','1');
p1/prescale_T(3) <= (p1/prescale(0) AND p1/prescale(1) AND p1/prescale(2));

FTCPE_p1/prescale4: FTCPE port map (p1/prescale(4),p1/prescale_T(4),CLK,'0','0','1');
p1/prescale_T(4) <= (p1/prescale(0) AND p1/prescale(1) AND p1/prescale(2) AND 
	p1/prescale(3));

FTCPE_postsc0: FTCPE port map (postsc(0),'0',orajel,'0','0','1');

FTCPE_postsc1: FTCPE port map (postsc(1),postsc(0),orajel,'0','0','1');

FTCPE_postsc2: FTCPE port map (postsc(2),postsc_T(2),orajel,'0','0','1');
postsc_T(2) <= (postsc(0) AND postsc(1));

FTCPE_postsc3: FTCPE port map (postsc(3),postsc_T(3),orajel,'0','0','1');
postsc_T(3) <= (postsc(0) AND postsc(1) AND postsc(2));

FTCPE_postsc4: FTCPE port map (postsc(4),postsc_T(4),orajel,'0','0','1');
postsc_T(4) <= (postsc(0) AND postsc(1) AND postsc(2) AND postsc(3));

FTCPE_postsc5: FTCPE port map (postsc(5),postsc_T(5),orajel,'0','0','1');
postsc_T(5) <= (postsc(0) AND postsc(1) AND postsc(2) AND postsc(3) AND 
	postsc(4));

FTCPE_postsc6: FTCPE port map (postsc(6),postsc_T(6),orajel,'0','0','1');
postsc_T(6) <= (postsc(0) AND postsc(1) AND postsc(2) AND postsc(3) AND 
	postsc(4) AND postsc(5));

FTCPE_postsc7: FTCPE port map (postsc(7),postsc_T(7),orajel,'0','0','1');
postsc_T(7) <= (postsc(0) AND postsc(1) AND postsc(2) AND postsc(3) AND 
	postsc(4) AND postsc(5) AND postsc(6));

FTCPE_postsc8: FTCPE port map (postsc(8),postsc_T(8),orajel,'0','0','1');
postsc_T(8) <= (postsc(0) AND postsc(1) AND postsc(2) AND postsc(3) AND 
	postsc(4) AND postsc(5) AND postsc(6) AND postsc(7));

FTCPE_postsc9: FTCPE port map (postsc(9),postsc_T(9),orajel,'0','0','1');
postsc_T(9) <= (postsc(0) AND postsc(1) AND postsc(2) AND postsc(3) AND 
	postsc(4) AND postsc(5) AND postsc(6) AND postsc(7) AND postsc(8));

FTCPE_postsc10: FTCPE port map (postsc(10),postsc_T(10),orajel,'0','0','1');
postsc_T(10) <= (postsc(0) AND postsc(1) AND postsc(2) AND postsc(3) AND 
	postsc(4) AND postsc(5) AND postsc(6) AND postsc(7) AND postsc(8) AND 
	postsc(9));

FTCPE_postsc11: FTCPE port map (postsc(11),postsc_T(11),orajel,'0','0','1');
postsc_T(11) <= (postsc(0) AND postsc(10) AND postsc(1) AND postsc(2) AND 
	postsc(3) AND postsc(4) AND postsc(5) AND postsc(6) AND postsc(7) AND 
	postsc(8) AND postsc(9));

FTCPE_postsc12: FTCPE port map (postsc(12),postsc_T(12),orajel,'0','0','1');
postsc_T(12) <= (postsc(0) AND postsc(10) AND postsc(1) AND postsc(2) AND 
	postsc(3) AND postsc(4) AND postsc(5) AND postsc(6) AND postsc(7) AND 
	postsc(8) AND postsc(9) AND postsc(11));

FTCPE_postsc13: FTCPE port map (postsc(13),postsc_T(13),orajel,'0','0','1');
postsc_T(13) <= (postsc(0) AND postsc(10) AND postsc(1) AND postsc(2) AND 
	postsc(3) AND postsc(4) AND postsc(5) AND postsc(6) AND postsc(7) AND 
	postsc(8) AND postsc(9) AND postsc(11) AND postsc(12));

FTCPE_postsc14: FTCPE port map (postsc(14),postsc_T(14),orajel,'0','0','1');
postsc_T(14) <= (postsc(0) AND postsc(10) AND postsc(1) AND postsc(2) AND 
	postsc(3) AND postsc(4) AND postsc(5) AND postsc(6) AND postsc(7) AND 
	postsc(8) AND postsc(9) AND postsc(11) AND postsc(12) AND 
	postsc(13));

FTCPE_postsc15: FTCPE port map (postsc(15),postsc_T(15),orajel,'0','0','1');
postsc_T(15) <= (postsc(0) AND postsc(10) AND postsc(1) AND postsc(2) AND 
	postsc(3) AND postsc(4) AND postsc(5) AND postsc(6) AND postsc(7) AND 
	postsc(8) AND postsc(9) AND postsc(11) AND postsc(12) AND 
	postsc(13) AND postsc(14));

FTCPE_r1/cbit0: FTCPE port map (r1/cbit(0),r1/cbit_T(0),orajel,'0','0','1');
r1/cbit_T(0) <= NOT (((r1/startb AND r1/csample(0))
	OR (r1/startb AND r1/csample(1))
	OR (NOT r1/startb AND NOT r1/cbit(0))
	OR (NOT r1/cbit(0) AND r1/cbit(1) AND NOT r1/cbit(2) AND 
	r1/cbit(3))));

FTCPE_r1/cbit1: FTCPE port map (r1/cbit(1),r1/cbit_T(1),orajel,'0','0','1');
r1/cbit_T(1) <= ((NOT r1/startb AND r1/cbit(1))
	OR (r1/startb AND r1/cbit(0) AND NOT r1/csample(0) AND 
	NOT r1/csample(1))
	OR (r1/cbit(1) AND NOT r1/csample(0) AND NOT r1/csample(1) AND 
	NOT r1/cbit(2) AND r1/cbit(3)));

FTCPE_r1/cbit2: FTCPE port map (r1/cbit(2),r1/cbit_T(2),orajel,'0','0','1');
r1/cbit_T(2) <= ((NOT r1/startb AND r1/cbit(2))
	OR (r1/startb AND r1/cbit(0) AND r1/cbit(1) AND 
	NOT r1/csample(0) AND NOT r1/csample(1)));

FTCPE_r1/cbit3: FTCPE port map (r1/cbit(3),r1/cbit_T(3),orajel,'0','0','1');
r1/cbit_T(3) <= ((NOT r1/startb AND r1/cbit(3))
	OR (r1/startb AND r1/cbit(0) AND r1/cbit(1) AND 
	NOT r1/csample(0) AND NOT r1/csample(1) AND r1/cbit(2))
	OR (NOT r1/cbit(0) AND r1/cbit(1) AND NOT r1/csample(0) AND 
	NOT r1/csample(1) AND NOT r1/cbit(2) AND r1/cbit(3)));

FDCPE_r1/csample0: FDCPE port map (r1/csample(0),r1/csample_D(0),orajel,'0','0','1');
r1/csample_D(0) <= (r1/startb AND NOT r1/csample(0) AND NOT r1/csample(1));

FDCPE_r1/csample1: FDCPE port map (r1/csample(1),r1/csample_D(1),orajel,'0','0','1');
r1/csample_D(1) <= (r1/startb AND r1/csample(0) AND NOT r1/csample(1));

FTCPE_r1/data8: FTCPE port map (r1/data(8),r1/data_T(8),orajel,'0','0','1');
r1/data_T(8) <= ((r1/data(8) AND r1/startb AND NOT r1/csample(0) AND 
	r1/csample(1) AND NOT r1/data(9))
	OR (NOT r1/data(8) AND r1/startb AND NOT r1/csample(0) AND 
	r1/csample(1) AND r1/data(9)));

FDCPE_r1/data9: FDCPE port map (r1/data(9),REC,orajel,'0','0',r1/data_CE(9));
r1/data_CE(9) <= (r1/startb AND NOT r1/csample(0) AND NOT r1/csample(1));

FDCPE_r1/startb: FDCPE port map (r1/startb,r1/startb_D,orajel,'0','0','1');
r1/startb_D <= NOT (((NOT r1/startb AND REC)
	OR (r1/startb AND NOT r1/cbit(0) AND r1/cbit(1) AND 
	NOT r1/csample(0) AND NOT r1/csample(1) AND NOT r1/cbit(2) AND r1/cbit(3))));

FTCPE_t1/bitsz0: FTCPE port map (t1/bitsz(0),t1/bitsz_T(0),orajel,'0','0','1');
t1/bitsz_T(0) <= ((trmt AND t1/bitsz(0))
	OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1)));

FTCPE_t1/bitsz1: FTCPE port map (t1/bitsz(1),t1/bitsz_T(1),orajel,'0','0','1');
t1/bitsz_T(1) <= ((trmt AND t1/bitsz(1))
	OR (tr_inproc AND NOT trmt AND t1/bitsz(0) AND NOT t1/div(0) AND 
	t1/div(1)));

FTCPE_t1/bitsz2: FTCPE port map (t1/bitsz(2),t1/bitsz_T(2),orajel,'0','0','1');
t1/bitsz_T(2) <= ((trmt AND t1/bitsz(2))
	OR (tr_inproc AND NOT trmt AND t1/bitsz(0) AND NOT t1/div(0) AND 
	t1/div(1) AND t1/bitsz(1)));

FTCPE_t1/bitsz3: FTCPE port map (t1/bitsz(3),t1/bitsz_T(3),orajel,'0','0','1');
t1/bitsz_T(3) <= ((trmt AND t1/bitsz(3))
	OR (tr_inproc AND NOT trmt AND t1/bitsz(0) AND NOT t1/div(0) AND 
	t1/div(1) AND t1/bitsz(1) AND t1/bitsz(2)));

FDCPE_t1/div0: FDCPE port map (t1/div(0),t1/div_D(0),orajel,'0','0','1');
t1/div_D(0) <= (NOT trmt AND NOT t1/div(0) AND NOT t1/div(1));

FDCPE_t1/div1: FDCPE port map (t1/div(1),t1/div_D(1),orajel,'0','0','1');
t1/div_D(1) <= (NOT trmt AND t1/div(0) AND NOT t1/div(1));

FTCPE_t1/shdata1: FTCPE port map (t1/shdata(1),t1/shdata_T(1),orajel,'0','0','1');
t1/shdata_T(1) <= ((trmt AND t1/shdata(1))
	OR (tr_inproc AND NOT t1/div(0) AND t1/div(1) AND 
	t1/shdata(1) AND NOT t1/shdata(2))
	OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND 
	NOT t1/shdata(1) AND t1/shdata(2)));

FTCPE_t1/shdata2: FTCPE port map (t1/shdata(2),t1/shdata_T(2),orajel,'0','0','1');
t1/shdata_T(2) <= ((trmt AND t1/shdata(2) AND NOT OUT(0))
	OR (trmt AND NOT t1/shdata(2) AND OUT(0))
	OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND 
	t1/shdata(2) AND NOT t1/shdata(3))
	OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND 
	NOT t1/shdata(2) AND t1/shdata(3)));

FTCPE_t1/shdata3: FTCPE port map (t1/shdata(3),t1/shdata_T(3),orajel,'0','0','1');
t1/shdata_T(3) <= ((OUT(1) AND trmt AND NOT t1/shdata(3))
	OR (NOT OUT(1) AND trmt AND t1/shdata(3))
	OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND 
	t1/shdata(3) AND NOT t1/shdata(4))
	OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND 
	NOT t1/shdata(3) AND t1/shdata(4)));

FTCPE_t1/shdata4: FTCPE port map (t1/shdata(4),t1/shdata_T(4),orajel,'0','0','1');
t1/shdata_T(4) <= ((OUT(2) AND trmt AND NOT t1/shdata(4))
	OR (NOT OUT(2) AND trmt AND t1/shdata(4))
	OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND 
	t1/shdata(4) AND NOT t1/shdata(5))
	OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND 
	NOT t1/shdata(4) AND t1/shdata(5)));

FTCPE_t1/shdata5: FTCPE port map (t1/shdata(5),t1/shdata_T(5),orajel,'0','0','1');
t1/shdata_T(5) <= ((OUT(3) AND trmt AND NOT t1/shdata(5))
	OR (NOT OUT(3) AND trmt AND t1/shdata(5))
	OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND 
	t1/shdata(5) AND NOT t1/shdata(6))
	OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND 
	NOT t1/shdata(5) AND t1/shdata(6)));

FTCPE_t1/shdata6: FTCPE port map (t1/shdata(6),t1/shdata_T(6),orajel,'0','0','1');
t1/shdata_T(6) <= ((OUT(4) AND trmt AND NOT t1/shdata(6))
	OR (NOT OUT(4) AND trmt AND t1/shdata(6))
	OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND 
	t1/shdata(6) AND NOT t1/shdata(7))
	OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND 
	NOT t1/shdata(6) AND t1/shdata(7)));

FTCPE_t1/shdata7: FTCPE port map (t1/shdata(7),t1/shdata_T(7),orajel,'0','0','1');
t1/shdata_T(7) <= ((OUT(5) AND trmt AND NOT t1/shdata(7))
	OR (NOT OUT(5) AND trmt AND t1/shdata(7))
	OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND 
	t1/shdata(7) AND NOT t1/shdata(8))
	OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND 
	NOT t1/shdata(7) AND t1/shdata(8)));

FTCPE_t1/shdata8: FTCPE port map (t1/shdata(8),t1/shdata_T(8),orajel,'0','0','1');
t1/shdata_T(8) <= ((OUT(6) AND trmt AND NOT t1/shdata(8))
	OR (NOT OUT(6) AND trmt AND t1/shdata(8))
	OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND 
	t1/shdata(8) AND NOT t1/shdata(9))
	OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND 
	NOT t1/shdata(8) AND t1/shdata(9)));

FDCPE_t1/shdata9: FDCPE port map (t1/shdata(9),t1/shdata_D(9),orajel,'0','0','1');
t1/shdata_D(9) <= ((OUT(7) AND trmt)
	OR (NOT trmt AND t1/shdata(9))
	OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1)));

FDCPE_tr_inproc: FDCPE port map (tr_inproc,trmt,orajel,'0','0',N_PZ_504);

FDCPE_trmt: FDCPE port map (trmt,trmt_D,orajel,'0','0','1');
trmt_D <= (NOT tr_inproc AND NOT BUTTON AND NOT postsc(0) AND NOT postsc(10) AND 
	NOT postsc(1) AND NOT postsc(2) AND NOT postsc(3) AND NOT postsc(4) AND NOT postsc(5) AND 
	NOT postsc(6) AND NOT postsc(7) AND NOT postsc(8) AND NOT postsc(9) AND NOT postsc(11) AND 
	NOT postsc(12) AND NOT postsc(13) AND NOT postsc(14) AND NOT postsc(15));


Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FDDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 FTDCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC2C256-7-TQ144


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 VCC                              73 VCCIO-3.3                     
  2 KPR                              74 KPR                           
  3 KPR                              75 KPR                           
  4 KPR                              76 KPR                           
  5 KPR                              77 KPR                           
  6 KPR                              78 KPR                           
  7 KPR                              79 KPR                           
  8 VCCAUX                           80 KPR                           
  9 KPR                              81 KPR                           
 10 KPR                              82 KPR                           
 11 KPR                              83 KPR                           
 12 KPR                              84 VCC                           
 13 KPR                              85 KPR                           
 14 KPR                              86 KPR                           
 15 KPR                              87 KPR                           
 16 KPR                              88 KPR                           
 17 KPR                              89 GND                           
 18 KPR                              90 GND                           
 19 KPR                              91 KPR                           
 20 KPR                              92 KPR                           
 21 KPR                              93 VCCIO-3.3                     
 22 KPR                              94 KPR                           
 23 KPR                              95 KPR                           
 24 OUT<7>                           96 KPR                           
 25 OUT<6>                           97 KPR                           
 26 OUT<5>                           98 KPR                           
 27 VCCIO-3.3                        99 GND                           
 28 OUT<4>                          100 KPR                           
 29 GND                             101 KPR                           
 30 OUT<3>                          102 KPR                           
 31 OUT<2>                          103 KPR                           
 32 OUT<1>                          104 KPR                           
 33 EN1                             105 KPR                           
 34 DIR1                            106 KPR                           
 35 OUT<0>                          107 KPR                           
 36 GND                             108 GND                           
 37 VCC                             109 VCCIO-3.3                     
 38 CLK                             110 KPR                           
 39 SEND                            111 KPR                           
 40 KPR                             112 KPR                           
 41 KPR                             113 KPR                           
 42 REC                             114 KPR                           
 43 KPR                             115 KPR                           
 44 KPR                             116 KPR                           
 45 KPR                             117 KPR                           
 46 KPR                             118 KPR                           
 47 GND                             119 KPR                           
 48 KPR                             120 KPR                           
 49 KPR                             121 KPR                           
 50 KPR                             122 TDO                           
 51 KPR                             123 GND                           
 52 KPR                             124 KPR                           
 53 KPR                             125 KPR                           
 54 KPR                             126 KPR                           
 55 VCCIO-3.3                       127 VCCIO-3.3                     
 56 KPR                             128 KPR                           
 57 KPR                             129 KPR                           
 58 KPR                             130 KPR                           
 59 KPR                             131 KPR                           
 60 KPR                             132 KPR                           
 61 KPR                             133 KPR                           
 62 GND                             134 KPR                           
 63 TDI                             135 KPR                           
 64 KPR                             136 KPR                           
 65 TMS                             137 KPR                           
 66 KPR                             138 KPR                           
 67 TCK                             139 KPR                           
 68 KPR                             140 KPR                           
 69 KPR                             141 VCCIO-3.3                     
 70 KPR                             142 KPR                           
 71 KPR                             143 BUTTON                        
 72 GND                             144 GND                           


Legend :  NC  = Not Connected, unbonded pin
        PGND  = Unused I/O configured as additional Ground pin
         KPR  = Unused I/O with weak keeper (leave unconnected)
         WPU  = Unused I/O with weak pull up (leave unconnected)
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
      VCCAUX  = Power supply for JTAG pins
   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
   VCCIO-1.8  = I/O supply voltage for LVCMOS18
   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
        VREF  = Reference voltage for indicated input standard
       *VREF  = Reference voltage pin selected by software
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc2c256-7-TQ144
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Set Unused I/O Pin Termination              : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Use DATA_GATE Attribute                     : ON
Set Tristate Outputs to Termination Mode    : KEEPER
Default Voltage Standard for All Outputs    : LVCMOS18
Input Limit                                 : 32
Pterm Limit                                 : 28