Equations

********** Mapped Logic **********
DIR1 <= NOT ('0');
EN1 <= '0';
N_PZ_372 <= (bus1(0) AND bus1(1) AND bus1(2) AND bus1(3) AND
      bus1(4));
N_PZ_504 <= ((trmt)
      OR (tr_inproc AND NOT t1/bitsz(0) AND NOT t1/div(0) AND t1/div(1) AND
      t1/bitsz(1) AND NOT t1/bitsz(2) AND t1/bitsz(3)));
FDCPE_OUT0: FDCPE port map (OUT(0),NOT bus1(0),orajel,'0','0',NOT r1/startb);
FDCPE_OUT1: FDCPE port map (OUT(1),OUT_D(1),orajel,'0','0','1');
     OUT_D(1) <= ((r1/startb AND OUT(1))
      OR (bus1(0) AND NOT bus1(1) AND NOT r1/startb)
      OR (NOT bus1(0) AND bus1(1) AND NOT r1/startb));
FDCPE_OUT2: FDCPE port map (OUT(2),OUT_D(2),orajel,'0','0','1');
     OUT_D(2) <= (bus1(2) AND NOT r1/startb)
      XOR ((r1/startb AND OUT(2))
      OR (bus1(0) AND bus1(1) AND NOT r1/startb));
FDCPE_OUT3: FDCPE port map (OUT(3),OUT_D(3),orajel,'0','0','1');
     OUT_D(3) <= (bus1(3) AND NOT r1/startb)
      XOR ((r1/startb AND OUT(3))
      OR (bus1(0) AND bus1(1) AND bus1(2) AND NOT r1/startb));
FDCPE_OUT4: FDCPE port map (OUT(4),OUT_D(4),orajel,'0','0','1');
     OUT_D(4) <= (bus1(4) AND NOT r1/startb)
      XOR ((r1/startb AND OUT(4))
      OR (bus1(0) AND bus1(1) AND bus1(2) AND bus1(3) AND
      NOT r1/startb));
FDCPE_OUT5: FDCPE port map (OUT(5),OUT_D(5),orajel,'0','0','1');
     OUT_D(5) <= ((r1/startb AND OUT(5))
      OR (bus1(5) AND NOT r1/startb AND NOT N_PZ_372)
      OR (NOT bus1(5) AND NOT r1/startb AND N_PZ_372));
FDCPE_OUT6: FDCPE port map (OUT(6),OUT_D(6),orajel,'0','0','1');
     OUT_D(6) <= (bus1(6) AND NOT r1/startb)
      XOR ((r1/startb AND OUT(6))
      OR (bus1(5) AND NOT r1/startb AND N_PZ_372));
FDCPE_OUT7: FDCPE port map (OUT(7),OUT_D(7),orajel,'0','0','1');
     OUT_D(7) <= (bus1(7) AND NOT r1/startb)
      XOR ((r1/startb AND OUT(7))
      OR (bus1(5) AND bus1(6) AND NOT r1/startb AND N_PZ_372));
FTCPE_SEND: FTCPE port map (SEND,SEND_T,orajel,'0','0','1');
     SEND_T <= ((NOT tr_inproc AND NOT trmt AND NOT SEND)
      OR (NOT trmt AND NOT t1/div(0) AND t1/div(1) AND t1/shdata(1) AND
      NOT SEND)
      OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND
      NOT t1/shdata(1) AND SEND));
FDCPE_bus10: FDCPE port map (bus1(0),bus1(1),orajel,'0','0',bus1_CE(0));
     bus1_CE(0) <= (r1/startb AND NOT r1/csample(0) AND r1/csample(1));
FDCPE_bus11: FDCPE port map (bus1(1),bus1(2),orajel,'0','0',bus1_CE(1));
     bus1_CE(1) <= (r1/startb AND NOT r1/csample(0) AND r1/csample(1));
FDCPE_bus12: FDCPE port map (bus1(2),bus1(3),orajel,'0','0',bus1_CE(2));
     bus1_CE(2) <= (r1/startb AND NOT r1/csample(0) AND r1/csample(1));
FDCPE_bus13: FDCPE port map (bus1(3),bus1(4),orajel,'0','0',bus1_CE(3));
     bus1_CE(3) <= (r1/startb AND NOT r1/csample(0) AND r1/csample(1));
FDCPE_bus14: FDCPE port map (bus1(4),bus1(5),orajel,'0','0',bus1_CE(4));
     bus1_CE(4) <= (r1/startb AND NOT r1/csample(0) AND r1/csample(1));
FDCPE_bus15: FDCPE port map (bus1(5),bus1(6),orajel,'0','0',bus1_CE(5));
     bus1_CE(5) <= (r1/startb AND NOT r1/csample(0) AND r1/csample(1));
FDCPE_bus16: FDCPE port map (bus1(6),bus1(7),orajel,'0','0',bus1_CE(6));
     bus1_CE(6) <= (r1/startb AND NOT r1/csample(0) AND r1/csample(1));
FDCPE_bus17: FDCPE port map (bus1(7),r1/data(8),orajel,'0','0',bus1_CE(7));
     bus1_CE(7) <= (r1/startb AND NOT r1/csample(0) AND r1/csample(1));
FDCPE_orajel: FDCPE port map (orajel,orajel_D,CLK,'0','0','1');
     orajel_D <= (p1/prescale(0) AND p1/prescale(1) AND p1/prescale(2) AND
      p1/prescale(3) AND p1/prescale(4));
FTCPE_p1/prescale0: FTCPE port map (p1/prescale(0),'0',CLK,'0','0','1');
FTCPE_p1/prescale1: FTCPE port map (p1/prescale(1),p1/prescale(0),CLK,'0','0','1');
FTCPE_p1/prescale2: FTCPE port map (p1/prescale(2),p1/prescale_T(2),CLK,'0','0','1');
     p1/prescale_T(2) <= (p1/prescale(0) AND p1/prescale(1));
FTCPE_p1/prescale3: FTCPE port map (p1/prescale(3),p1/prescale_T(3),CLK,'0','0','1');
     p1/prescale_T(3) <= (p1/prescale(0) AND p1/prescale(1) AND p1/prescale(2));
FTCPE_p1/prescale4: FTCPE port map (p1/prescale(4),p1/prescale_T(4),CLK,'0','0','1');
     p1/prescale_T(4) <= (p1/prescale(0) AND p1/prescale(1) AND p1/prescale(2) AND
      p1/prescale(3));
FTCPE_postsc0: FTCPE port map (postsc(0),'0',orajel,'0','0','1');
FTCPE_postsc1: FTCPE port map (postsc(1),postsc(0),orajel,'0','0','1');
FTCPE_postsc2: FTCPE port map (postsc(2),postsc_T(2),orajel,'0','0','1');
     postsc_T(2) <= (postsc(0) AND postsc(1));
FTCPE_postsc3: FTCPE port map (postsc(3),postsc_T(3),orajel,'0','0','1');
     postsc_T(3) <= (postsc(0) AND postsc(1) AND postsc(2));
FTCPE_postsc4: FTCPE port map (postsc(4),postsc_T(4),orajel,'0','0','1');
     postsc_T(4) <= (postsc(0) AND postsc(1) AND postsc(2) AND postsc(3));
FTCPE_postsc5: FTCPE port map (postsc(5),postsc_T(5),orajel,'0','0','1');
     postsc_T(5) <= (postsc(0) AND postsc(1) AND postsc(2) AND postsc(3) AND
      postsc(4));
FTCPE_postsc6: FTCPE port map (postsc(6),postsc_T(6),orajel,'0','0','1');
     postsc_T(6) <= (postsc(0) AND postsc(1) AND postsc(2) AND postsc(3) AND
      postsc(4) AND postsc(5));
FTCPE_postsc7: FTCPE port map (postsc(7),postsc_T(7),orajel,'0','0','1');
     postsc_T(7) <= (postsc(0) AND postsc(1) AND postsc(2) AND postsc(3) AND
      postsc(4) AND postsc(5) AND postsc(6));
FTCPE_postsc8: FTCPE port map (postsc(8),postsc_T(8),orajel,'0','0','1');
     postsc_T(8) <= (postsc(0) AND postsc(1) AND postsc(2) AND postsc(3) AND
      postsc(4) AND postsc(5) AND postsc(6) AND postsc(7));
FTCPE_postsc9: FTCPE port map (postsc(9),postsc_T(9),orajel,'0','0','1');
     postsc_T(9) <= (postsc(0) AND postsc(1) AND postsc(2) AND postsc(3) AND
      postsc(4) AND postsc(5) AND postsc(6) AND postsc(7) AND postsc(8));
FTCPE_postsc10: FTCPE port map (postsc(10),postsc_T(10),orajel,'0','0','1');
     postsc_T(10) <= (postsc(0) AND postsc(1) AND postsc(2) AND postsc(3) AND
      postsc(4) AND postsc(5) AND postsc(6) AND postsc(7) AND postsc(8) AND
      postsc(9));
FTCPE_postsc11: FTCPE port map (postsc(11),postsc_T(11),orajel,'0','0','1');
     postsc_T(11) <= (postsc(0) AND postsc(10) AND postsc(1) AND postsc(2) AND
      postsc(3) AND postsc(4) AND postsc(5) AND postsc(6) AND postsc(7) AND
      postsc(8) AND postsc(9));
FTCPE_postsc12: FTCPE port map (postsc(12),postsc_T(12),orajel,'0','0','1');
     postsc_T(12) <= (postsc(0) AND postsc(10) AND postsc(1) AND postsc(2) AND
      postsc(3) AND postsc(4) AND postsc(5) AND postsc(6) AND postsc(7) AND
      postsc(8) AND postsc(9) AND postsc(11));
FTCPE_postsc13: FTCPE port map (postsc(13),postsc_T(13),orajel,'0','0','1');
     postsc_T(13) <= (postsc(0) AND postsc(10) AND postsc(1) AND postsc(2) AND
      postsc(3) AND postsc(4) AND postsc(5) AND postsc(6) AND postsc(7) AND
      postsc(8) AND postsc(9) AND postsc(11) AND postsc(12));
FTCPE_postsc14: FTCPE port map (postsc(14),postsc_T(14),orajel,'0','0','1');
     postsc_T(14) <= (postsc(0) AND postsc(10) AND postsc(1) AND postsc(2) AND
      postsc(3) AND postsc(4) AND postsc(5) AND postsc(6) AND postsc(7) AND
      postsc(8) AND postsc(9) AND postsc(11) AND postsc(12) AND
      postsc(13));
FTCPE_postsc15: FTCPE port map (postsc(15),postsc_T(15),orajel,'0','0','1');
     postsc_T(15) <= (postsc(0) AND postsc(10) AND postsc(1) AND postsc(2) AND
      postsc(3) AND postsc(4) AND postsc(5) AND postsc(6) AND postsc(7) AND
      postsc(8) AND postsc(9) AND postsc(11) AND postsc(12) AND
      postsc(13) AND postsc(14));
FTCPE_r1/cbit0: FTCPE port map (r1/cbit(0),r1/cbit_T(0),orajel,'0','0','1');
     r1/cbit_T(0) <= NOT (((r1/startb AND r1/csample(0))
      OR (r1/startb AND r1/csample(1))
      OR (NOT r1/startb AND NOT r1/cbit(0))
      OR (NOT r1/cbit(0) AND r1/cbit(1) AND NOT r1/cbit(2) AND
      r1/cbit(3))));
FTCPE_r1/cbit1: FTCPE port map (r1/cbit(1),r1/cbit_T(1),orajel,'0','0','1');
     r1/cbit_T(1) <= ((NOT r1/startb AND r1/cbit(1))
      OR (r1/startb AND r1/cbit(0) AND NOT r1/csample(0) AND
      NOT r1/csample(1))
      OR (r1/cbit(1) AND NOT r1/csample(0) AND NOT r1/csample(1) AND
      NOT r1/cbit(2) AND r1/cbit(3)));
FTCPE_r1/cbit2: FTCPE port map (r1/cbit(2),r1/cbit_T(2),orajel,'0','0','1');
     r1/cbit_T(2) <= ((NOT r1/startb AND r1/cbit(2))
      OR (r1/startb AND r1/cbit(0) AND r1/cbit(1) AND
      NOT r1/csample(0) AND NOT r1/csample(1)));
FTCPE_r1/cbit3: FTCPE port map (r1/cbit(3),r1/cbit_T(3),orajel,'0','0','1');
     r1/cbit_T(3) <= ((NOT r1/startb AND r1/cbit(3))
      OR (r1/startb AND r1/cbit(0) AND r1/cbit(1) AND
      NOT r1/csample(0) AND NOT r1/csample(1) AND r1/cbit(2))
      OR (NOT r1/cbit(0) AND r1/cbit(1) AND NOT r1/csample(0) AND
      NOT r1/csample(1) AND NOT r1/cbit(2) AND r1/cbit(3)));
FDCPE_r1/csample0: FDCPE port map (r1/csample(0),r1/csample_D(0),orajel,'0','0','1');
     r1/csample_D(0) <= (r1/startb AND NOT r1/csample(0) AND NOT r1/csample(1));
FDCPE_r1/csample1: FDCPE port map (r1/csample(1),r1/csample_D(1),orajel,'0','0','1');
     r1/csample_D(1) <= (r1/startb AND r1/csample(0) AND NOT r1/csample(1));
FTCPE_r1/data8: FTCPE port map (r1/data(8),r1/data_T(8),orajel,'0','0','1');
     r1/data_T(8) <= ((r1/data(8) AND r1/startb AND NOT r1/csample(0) AND
      r1/csample(1) AND NOT r1/data(9))
      OR (NOT r1/data(8) AND r1/startb AND NOT r1/csample(0) AND
      r1/csample(1) AND r1/data(9)));
FDCPE_r1/data9: FDCPE port map (r1/data(9),REC,orajel,'0','0',r1/data_CE(9));
     r1/data_CE(9) <= (r1/startb AND NOT r1/csample(0) AND NOT r1/csample(1));
FDCPE_r1/startb: FDCPE port map (r1/startb,r1/startb_D,orajel,'0','0','1');
     r1/startb_D <= NOT (((NOT r1/startb AND REC)
      OR (r1/startb AND NOT r1/cbit(0) AND r1/cbit(1) AND
      NOT r1/csample(0) AND NOT r1/csample(1) AND NOT r1/cbit(2) AND r1/cbit(3))));
FTCPE_t1/bitsz0: FTCPE port map (t1/bitsz(0),t1/bitsz_T(0),orajel,'0','0','1');
     t1/bitsz_T(0) <= ((trmt AND t1/bitsz(0))
      OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1)));
FTCPE_t1/bitsz1: FTCPE port map (t1/bitsz(1),t1/bitsz_T(1),orajel,'0','0','1');
     t1/bitsz_T(1) <= ((trmt AND t1/bitsz(1))
      OR (tr_inproc AND NOT trmt AND t1/bitsz(0) AND NOT t1/div(0) AND
      t1/div(1)));
FTCPE_t1/bitsz2: FTCPE port map (t1/bitsz(2),t1/bitsz_T(2),orajel,'0','0','1');
     t1/bitsz_T(2) <= ((trmt AND t1/bitsz(2))
      OR (tr_inproc AND NOT trmt AND t1/bitsz(0) AND NOT t1/div(0) AND
      t1/div(1) AND t1/bitsz(1)));
FTCPE_t1/bitsz3: FTCPE port map (t1/bitsz(3),t1/bitsz_T(3),orajel,'0','0','1');
     t1/bitsz_T(3) <= ((trmt AND t1/bitsz(3))
      OR (tr_inproc AND NOT trmt AND t1/bitsz(0) AND NOT t1/div(0) AND
      t1/div(1) AND t1/bitsz(1) AND t1/bitsz(2)));
FDCPE_t1/div0: FDCPE port map (t1/div(0),t1/div_D(0),orajel,'0','0','1');
     t1/div_D(0) <= (NOT trmt AND NOT t1/div(0) AND NOT t1/div(1));
FDCPE_t1/div1: FDCPE port map (t1/div(1),t1/div_D(1),orajel,'0','0','1');
     t1/div_D(1) <= (NOT trmt AND t1/div(0) AND NOT t1/div(1));
FTCPE_t1/shdata1: FTCPE port map (t1/shdata(1),t1/shdata_T(1),orajel,'0','0','1');
     t1/shdata_T(1) <= ((trmt AND t1/shdata(1))
      OR (tr_inproc AND NOT t1/div(0) AND t1/div(1) AND
      t1/shdata(1) AND NOT t1/shdata(2))
      OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND
      NOT t1/shdata(1) AND t1/shdata(2)));
FTCPE_t1/shdata2: FTCPE port map (t1/shdata(2),t1/shdata_T(2),orajel,'0','0','1');
     t1/shdata_T(2) <= ((trmt AND t1/shdata(2) AND NOT OUT(0))
      OR (trmt AND NOT t1/shdata(2) AND OUT(0))
      OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND
      t1/shdata(2) AND NOT t1/shdata(3))
      OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND
      NOT t1/shdata(2) AND t1/shdata(3)));
FTCPE_t1/shdata3: FTCPE port map (t1/shdata(3),t1/shdata_T(3),orajel,'0','0','1');
     t1/shdata_T(3) <= ((OUT(1) AND trmt AND NOT t1/shdata(3))
      OR (NOT OUT(1) AND trmt AND t1/shdata(3))
      OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND
      t1/shdata(3) AND NOT t1/shdata(4))
      OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND
      NOT t1/shdata(3) AND t1/shdata(4)));
FTCPE_t1/shdata4: FTCPE port map (t1/shdata(4),t1/shdata_T(4),orajel,'0','0','1');
     t1/shdata_T(4) <= ((OUT(2) AND trmt AND NOT t1/shdata(4))
      OR (NOT OUT(2) AND trmt AND t1/shdata(4))
      OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND
      t1/shdata(4) AND NOT t1/shdata(5))
      OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND
      NOT t1/shdata(4) AND t1/shdata(5)));
FTCPE_t1/shdata5: FTCPE port map (t1/shdata(5),t1/shdata_T(5),orajel,'0','0','1');
     t1/shdata_T(5) <= ((OUT(3) AND trmt AND NOT t1/shdata(5))
      OR (NOT OUT(3) AND trmt AND t1/shdata(5))
      OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND
      t1/shdata(5) AND NOT t1/shdata(6))
      OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND
      NOT t1/shdata(5) AND t1/shdata(6)));
FTCPE_t1/shdata6: FTCPE port map (t1/shdata(6),t1/shdata_T(6),orajel,'0','0','1');
     t1/shdata_T(6) <= ((OUT(4) AND trmt AND NOT t1/shdata(6))
      OR (NOT OUT(4) AND trmt AND t1/shdata(6))
      OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND
      t1/shdata(6) AND NOT t1/shdata(7))
      OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND
      NOT t1/shdata(6) AND t1/shdata(7)));
FTCPE_t1/shdata7: FTCPE port map (t1/shdata(7),t1/shdata_T(7),orajel,'0','0','1');
     t1/shdata_T(7) <= ((OUT(5) AND trmt AND NOT t1/shdata(7))
      OR (NOT OUT(5) AND trmt AND t1/shdata(7))
      OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND
      t1/shdata(7) AND NOT t1/shdata(8))
      OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND
      NOT t1/shdata(7) AND t1/shdata(8)));
FTCPE_t1/shdata8: FTCPE port map (t1/shdata(8),t1/shdata_T(8),orajel,'0','0','1');
     t1/shdata_T(8) <= ((OUT(6) AND trmt AND NOT t1/shdata(8))
      OR (NOT OUT(6) AND trmt AND t1/shdata(8))
      OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND
      t1/shdata(8) AND NOT t1/shdata(9))
      OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1) AND
      NOT t1/shdata(8) AND t1/shdata(9)));
FDCPE_t1/shdata9: FDCPE port map (t1/shdata(9),t1/shdata_D(9),orajel,'0','0','1');
     t1/shdata_D(9) <= ((OUT(7) AND trmt)
      OR (NOT trmt AND t1/shdata(9))
      OR (tr_inproc AND NOT trmt AND NOT t1/div(0) AND t1/div(1)));
FDCPE_tr_inproc: FDCPE port map (tr_inproc,trmt,orajel,'0','0',N_PZ_504);
FDCPE_trmt: FDCPE port map (trmt,trmt_D,orajel,'0','0','1');
     trmt_D <= (NOT tr_inproc AND NOT BUTTON AND NOT postsc(0) AND NOT postsc(10) AND
      NOT postsc(1) AND NOT postsc(2) AND NOT postsc(3) AND NOT postsc(4) AND NOT postsc(5) AND
      NOT postsc(6) AND NOT postsc(7) AND NOT postsc(8) AND NOT postsc(9) AND NOT postsc(11) AND
      NOT postsc(12) AND NOT postsc(13) AND NOT postsc(14) AND NOT postsc(15));
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FDDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      FTDCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);