Logic

Signal Name Total Pterms Total Inputs Function Block Macrocell Slew Rate Bank Pin Number Pin Type Pin Use Reg Use I/O Std I/O Style Reg Init State
t1/shdata<6> 5 8 FB2 MC1   2 2 I/O/GTS2 (b) TFF     RESET
t1/shdata<7> 5 8 FB2 MC3   2 3 I/O/GTS3 (b) TFF     RESET
t1/shdata<8> 5 8 FB2 MC4   2 4 I/O (b) TFF     RESET
t1/shdata<9> 4 7 FB2 MC5   2 5 I/O/GTS0 (b) DFF     RESET
N_PZ_504 2 8 FB2 MC12   2 6 I/O/GTS1 (b)        
t1/bitsz<3> 3 9 FB2 MC13   2 7 I/O (b) TFF     RESET
t1/bitsz<2> 3 8 FB2 MC14   2 9 I/O (b) TFF     RESET
t1/bitsz<1> 3 7 FB2 MC15   2 10 I/O (b) TFF     RESET
r1/data<8> 3 6 FB4 MC14   2 18 I/O (b) TFF     RESET
OUT<7> 4 7 FB7 MC11 FAST 1 24 I/O O DFF LVCMOS33   RESET
OUT<6> 4 6 FB7 MC6 FAST 1 25 I/O O DFF LVCMOS33   RESET
OUT<5> 4 5 FB7 MC5 FAST 1 26 I/O O DFF LVCMOS33   RESET
OUT<4> 4 8 FB5 MC14 FAST 1 28 I/O O DFF LVCMOS33   RESET
OUT<3> 4 7 FB5 MC6 FAST 1 30 I/O/GCK0 O DFF LVCMOS33   RESET
OUT<2> 4 6 FB5 MC5 FAST 1 31 I/O O DFF LVCMOS33   RESET
OUT<1> 4 5 FB5 MC4 FAST 1 32 I/O/GCK1 O DFF LVCMOS33   RESET
EN1 0 0 FB5 MC2 FAST 1 33 I/O O   LVCMOS33    
DIR1 0 0 FB6 MC1 FAST 1 34 I/O O   LVCMOS33    
OUT<0> 3 3 FB6 MC2 FAST 1 35 I/O/CDR O DEFF LVCMOS33   RESET
SEND 4 7 FB6 MC12 FAST 1 39 I/O/DGE O TFF LVCMOS33   RESET
r1/data<9> 2 4 FB6 MC15   1 42 I/O IR DEFF   KPR  
bus1<3> 3 5 FB3 MC16   2 131 I/O (b) DEFF     RESET
N_PZ_372 1 5 FB3 MC14   2 132 I/O (b)        
bus1<4> 3 5 FB3 MC5   2 133 I/O (b) DEFF     RESET
bus1<5> 3 5 FB3 MC3   2 134 I/O (b) DEFF     RESET
bus1<6> 3 5 FB3 MC2   2 135 I/O (b) DEFF     RESET
bus1<7> 3 5 FB3 MC1   2 136 I/O (b) DEFF     RESET
postsc<4> 2 5 FB1 MC14   2 137 I/O (b) TFF     RESET
postsc<5> 2 6 FB1 MC13   2 138 I/O (b) TFF     RESET
postsc<6> 2 7 FB1 MC12   2 139 I/O (b) TFF     RESET
postsc<7> 2 8 FB1 MC6   2 140 I/O (b) TFF     RESET
postsc<8> 2 9 FB1 MC4   2 142 I/O (b) TFF     RESET
postsc<9> 2 10 FB1 MC3   2 143 I/O/GSR I TFF   KPR RESET
postsc<3> 2 4 FB1 MC1       (b) (b)       RESET
postsc<2> 2 3 FB1 MC2       (b) (b)       RESET
postsc<1> 2 2 FB1 MC5       (b) (b)       RESET
postsc<0> 1 1 FB1 MC7       (b) (b)       RESET
orajel 1 5 FB1 MC8       (b) (b)       RESET
p1/prescale<4> 1 4 FB1 MC9       (b) (b)       RESET
p1/prescale<3> 1 3 FB1 MC10       (b) (b)       RESET
p1/prescale<2> 1 2 FB1 MC11       (b) (b)       RESET
p1/prescale<1> 1 1 FB1 MC15       (b) (b)       RESET
p1/prescale<0> 0 0 FB1 MC16       (b) (b)       RESET
t1/bitsz<0> 3 6 FB2 MC2       (b) (b)       RESET
postsc<10> 2 11 FB2 MC6       (b) (b)       RESET
postsc<11> 2 12 FB2 MC7       (b) (b)       RESET
postsc<12> 2 13 FB2 MC8       (b) (b)       RESET
postsc<13> 2 14 FB2 MC9       (b) (b)       RESET
postsc<14> 2 15 FB2 MC10       (b) (b)       RESET
postsc<15> 2 16 FB2 MC11       (b) (b)       RESET
trmt 2 19 FB2 MC16       (b) (b)       RESET
bus1<2> 3 5 FB3 MC4       (b) (b)       RESET
bus1<1> 3 5 FB3 MC6       (b) (b)       RESET
bus1<0> 3 5 FB3 MC7       (b) (b)       RESET
r1/csample<1> 2 4 FB3 MC8       (b) (b)       RESET
r1/csample<0> 2 4 FB3 MC9       (b) (b)       RESET
r1/cbit<2> 3 7 FB3 MC10       (b) (b)       RESET
r1/cbit<0> 5 8 FB3 MC11       (b) (b)       RESET
r1/cbit<3> 4 8 FB3 MC12       (b) (b)       RESET
r1/cbit<1> 4 8 FB3 MC13       (b) (b)       RESET
r1/startb 3 9 FB3 MC15       (b) (b)       RESET
tr_inproc 3 3 FB4 MC7       (b) (b)       RESET
t1/div<1> 2 4 FB4 MC8       (b) (b)       RESET
t1/div<0> 2 4 FB4 MC9       (b) (b)       RESET
t1/shdata<5> 5 8 FB4 MC10       (b) (b)       RESET
t1/shdata<4> 5 8 FB4 MC11       (b) (b)       RESET
t1/shdata<3> 5 8 FB4 MC13       (b) (b)       RESET
t1/shdata<1> 4 7 FB4 MC15       (b) (b)       RESET
t1/shdata<2> 5 8 FB4 MC16       (b) (b)       RESET