Design Name | kiserlet_top |
Device, Speed (SpeedFile Version) | XC2C256, -7 (14.0 Advance Product Specification) |
Date Created | Sat May 19 21:18:25 2007 |
Created By | Timing Report Generator: version I.31 |
Copyright | Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. |
Performance Summary | |
---|---|
Min. Clock Period | 12.200 ns. |
Max. Clock Frequency (fSYSTEM) | 81.967 MHz. |
Limited by Cycle Time for orajel_MC.Q | |
Clock to Setup (tCYC) | 12.200 ns. |
Setup to Clock at the Pad (tSU) | 1.600 ns. |
Clock Pad to Output Pad Delay (tCO) | 13.400 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
TS_CLK | 0.0 | 6.6 | 15 | 15 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
p1/prescale<0>.Q to orajel.D | 0.000 | 6.600 | -6.600 |
p1/prescale<0>.Q to p1/prescale<1>.D | 0.000 | 6.600 | -6.600 |
p1/prescale<0>.Q to p1/prescale<2>.D | 0.000 | 6.600 | -6.600 |
Clock | fEXT (MHz) | Reason |
---|---|---|
CLK | 151.515 | Limited by Cycle Time for CLK |
orajel_MC.Q | 81.967 | Limited by Cycle Time for orajel_MC.Q |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
BUTTON | 1.100 | 0.000 |
REC | 1.600 | 0.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
OUT<0> | 13.400 |
OUT<1> | 13.400 |
OUT<2> | 13.400 |
OUT<3> | 13.400 |
OUT<4> | 13.400 |
OUT<5> | 13.400 |
OUT<6> | 13.400 |
OUT<7> | 13.400 |
SEND | 13.400 |
Source | Destination | Delay |
---|---|---|
p1/prescale<0>.Q | orajel.D | 6.600 |
p1/prescale<0>.Q | p1/prescale<1>.D | 6.600 |
p1/prescale<0>.Q | p1/prescale<2>.D | 6.600 |
p1/prescale<0>.Q | p1/prescale<3>.D | 6.600 |
p1/prescale<0>.Q | p1/prescale<4>.D | 6.600 |
p1/prescale<1>.Q | orajel.D | 6.600 |
p1/prescale<1>.Q | p1/prescale<2>.D | 6.600 |
p1/prescale<1>.Q | p1/prescale<3>.D | 6.600 |
p1/prescale<1>.Q | p1/prescale<4>.D | 6.600 |
p1/prescale<2>.Q | orajel.D | 6.600 |
p1/prescale<2>.Q | p1/prescale<3>.D | 6.600 |
p1/prescale<2>.Q | p1/prescale<4>.D | 6.600 |
p1/prescale<3>.Q | orajel.D | 6.600 |
p1/prescale<3>.Q | p1/prescale<4>.D | 6.600 |
p1/prescale<4>.Q | orajel.D | 6.600 |
Source | Destination | Delay |
---|---|---|
t1/bitsz<0>.Q | tr_inproc.CE | 12.200 |
t1/bitsz<1>.Q | tr_inproc.CE | 12.200 |
t1/bitsz<2>.Q | tr_inproc.CE | 12.200 |
t1/bitsz<3>.Q | tr_inproc.CE | 12.200 |
t1/div<0>.Q | tr_inproc.CE | 12.200 |
t1/div<1>.Q | tr_inproc.CE | 12.200 |
tr_inproc.Q | tr_inproc.CE | 12.200 |
trmt.Q | tr_inproc.CE | 12.200 |
bus1<0>.Q | OUT<5>.D | 11.900 |
bus1<0>.Q | OUT<6>.D | 11.900 |
bus1<0>.Q | OUT<7>.D | 11.900 |
bus1<1>.Q | OUT<5>.D | 11.900 |
bus1<1>.Q | OUT<6>.D | 11.900 |
bus1<1>.Q | OUT<7>.D | 11.900 |
bus1<2>.Q | OUT<5>.D | 11.900 |
bus1<2>.Q | OUT<6>.D | 11.900 |
bus1<2>.Q | OUT<7>.D | 11.900 |
bus1<3>.Q | OUT<5>.D | 11.900 |
bus1<3>.Q | OUT<6>.D | 11.900 |
bus1<3>.Q | OUT<7>.D | 11.900 |
bus1<4>.Q | OUT<5>.D | 11.900 |
bus1<4>.Q | OUT<6>.D | 11.900 |
bus1<4>.Q | OUT<7>.D | 11.900 |
OUT<0>.Q | t1/shdata<2>.D | 7.100 |
OUT<1>.Q | OUT<1>.D | 7.100 |
OUT<1>.Q | t1/shdata<3>.D | 7.100 |
OUT<2>.Q | OUT<2>.D | 7.100 |
OUT<2>.Q | t1/shdata<4>.D | 7.100 |
OUT<3>.Q | OUT<3>.D | 7.100 |
OUT<3>.Q | t1/shdata<5>.D | 7.100 |
OUT<4>.Q | OUT<4>.D | 7.100 |
OUT<4>.Q | t1/shdata<6>.D | 7.100 |
OUT<5>.Q | OUT<5>.D | 7.100 |
OUT<5>.Q | t1/shdata<7>.D | 7.100 |
OUT<6>.Q | OUT<6>.D | 7.100 |
OUT<6>.Q | t1/shdata<8>.D | 7.100 |
OUT<7>.Q | OUT<7>.D | 7.100 |
OUT<7>.Q | t1/shdata<9>.D | 7.100 |
SEND.Q | SEND.D | 7.100 |
bus1<0>.Q | OUT<0>.D | 7.100 |
bus1<0>.Q | OUT<1>.D | 7.100 |
bus1<0>.Q | OUT<2>.D | 7.100 |
bus1<0>.Q | OUT<3>.D | 7.100 |
bus1<0>.Q | OUT<4>.D | 7.100 |
bus1<1>.Q | OUT<1>.D | 7.100 |
bus1<1>.Q | OUT<2>.D | 7.100 |
bus1<1>.Q | OUT<3>.D | 7.100 |
bus1<1>.Q | OUT<4>.D | 7.100 |
bus1<1>.Q | bus1<0>.D | 7.100 |
bus1<2>.Q | OUT<3>.D | 7.100 |
bus1<2>.Q | OUT<4>.D | 7.100 |
bus1<2>.Q | bus1<1>.D | 7.100 |
bus1<3>.Q | OUT<4>.D | 7.100 |
bus1<3>.Q | bus1<2>.D | 7.100 |
bus1<4>.Q | bus1<3>.D | 7.100 |
bus1<5>.Q | OUT<5>.D | 7.100 |
bus1<5>.Q | OUT<6>.D | 7.100 |
bus1<5>.Q | OUT<7>.D | 7.100 |
bus1<5>.Q | bus1<4>.D | 7.100 |
bus1<6>.Q | OUT<7>.D | 7.100 |
bus1<6>.Q | bus1<5>.D | 7.100 |
bus1<7>.Q | bus1<6>.D | 7.100 |
r1/cbit<0>.Q | r1/cbit<0>.D | 7.100 |
r1/cbit<0>.Q | r1/cbit<1>.D | 7.100 |
r1/cbit<0>.Q | r1/cbit<2>.D | 7.100 |
r1/cbit<0>.Q | r1/cbit<3>.D | 7.100 |
r1/cbit<0>.Q | r1/startb.D | 7.100 |
r1/cbit<1>.Q | r1/cbit<0>.D | 7.100 |
r1/cbit<1>.Q | r1/cbit<1>.D | 7.100 |
r1/cbit<1>.Q | r1/cbit<2>.D | 7.100 |
r1/cbit<1>.Q | r1/cbit<3>.D | 7.100 |
r1/cbit<1>.Q | r1/startb.D | 7.100 |
r1/cbit<2>.Q | r1/cbit<0>.D | 7.100 |
r1/cbit<2>.Q | r1/cbit<1>.D | 7.100 |
r1/cbit<2>.Q | r1/cbit<2>.D | 7.100 |
r1/cbit<2>.Q | r1/cbit<3>.D | 7.100 |
r1/cbit<2>.Q | r1/startb.D | 7.100 |
r1/cbit<3>.Q | r1/cbit<0>.D | 7.100 |
r1/cbit<3>.Q | r1/cbit<1>.D | 7.100 |
r1/cbit<3>.Q | r1/cbit<3>.D | 7.100 |
r1/cbit<3>.Q | r1/startb.D | 7.100 |
r1/csample<0>.Q | r1/cbit<0>.D | 7.100 |
r1/csample<0>.Q | r1/cbit<1>.D | 7.100 |
r1/csample<0>.Q | r1/cbit<2>.D | 7.100 |
r1/csample<0>.Q | r1/cbit<3>.D | 7.100 |
r1/csample<0>.Q | r1/data<8>.D | 7.100 |
r1/csample<0>.Q | r1/startb.D | 7.100 |
r1/csample<1>.Q | r1/cbit<0>.D | 7.100 |
r1/csample<1>.Q | r1/cbit<1>.D | 7.100 |
r1/csample<1>.Q | r1/cbit<2>.D | 7.100 |
r1/csample<1>.Q | r1/cbit<3>.D | 7.100 |
r1/csample<1>.Q | r1/data<8>.D | 7.100 |
r1/csample<1>.Q | r1/startb.D | 7.100 |
r1/data<8>.Q | bus1<7>.D | 7.100 |
r1/data<8>.Q | r1/data<8>.D | 7.100 |
r1/data<9>.Q | r1/data<8>.D | 7.100 |
r1/startb.Q | OUT<1>.D | 7.100 |
r1/startb.Q | OUT<2>.D | 7.100 |
r1/startb.Q | OUT<3>.D | 7.100 |
r1/startb.Q | OUT<4>.D | 7.100 |
r1/startb.Q | OUT<5>.D | 7.100 |
r1/startb.Q | OUT<6>.D | 7.100 |
r1/startb.Q | OUT<7>.D | 7.100 |
r1/startb.Q | r1/cbit<0>.D | 7.100 |
r1/startb.Q | r1/cbit<1>.D | 7.100 |
r1/startb.Q | r1/cbit<2>.D | 7.100 |
r1/startb.Q | r1/cbit<3>.D | 7.100 |
r1/startb.Q | r1/data<8>.D | 7.100 |
r1/startb.Q | r1/startb.D | 7.100 |
t1/bitsz<0>.Q | t1/bitsz<0>.D | 7.100 |
t1/bitsz<0>.Q | t1/bitsz<1>.D | 7.100 |
t1/bitsz<0>.Q | t1/bitsz<2>.D | 7.100 |
t1/bitsz<0>.Q | t1/bitsz<3>.D | 7.100 |
t1/bitsz<1>.Q | t1/bitsz<1>.D | 7.100 |
t1/bitsz<1>.Q | t1/bitsz<2>.D | 7.100 |
t1/bitsz<1>.Q | t1/bitsz<3>.D | 7.100 |
t1/bitsz<2>.Q | t1/bitsz<2>.D | 7.100 |
t1/bitsz<2>.Q | t1/bitsz<3>.D | 7.100 |
t1/bitsz<3>.Q | t1/bitsz<3>.D | 7.100 |
t1/div<0>.Q | SEND.D | 7.100 |
t1/div<0>.Q | t1/bitsz<0>.D | 7.100 |
t1/div<0>.Q | t1/bitsz<1>.D | 7.100 |
t1/div<0>.Q | t1/bitsz<2>.D | 7.100 |
t1/div<0>.Q | t1/bitsz<3>.D | 7.100 |
t1/div<0>.Q | t1/shdata<1>.D | 7.100 |
t1/div<0>.Q | t1/shdata<2>.D | 7.100 |
t1/div<0>.Q | t1/shdata<3>.D | 7.100 |
t1/div<0>.Q | t1/shdata<4>.D | 7.100 |
t1/div<0>.Q | t1/shdata<5>.D | 7.100 |
t1/div<0>.Q | t1/shdata<6>.D | 7.100 |
t1/div<0>.Q | t1/shdata<7>.D | 7.100 |
t1/div<0>.Q | t1/shdata<8>.D | 7.100 |
t1/div<0>.Q | t1/shdata<9>.D | 7.100 |
t1/div<1>.Q | SEND.D | 7.100 |
t1/div<1>.Q | t1/bitsz<0>.D | 7.100 |
t1/div<1>.Q | t1/bitsz<1>.D | 7.100 |
t1/div<1>.Q | t1/bitsz<2>.D | 7.100 |
t1/div<1>.Q | t1/bitsz<3>.D | 7.100 |
t1/div<1>.Q | t1/shdata<1>.D | 7.100 |
t1/div<1>.Q | t1/shdata<2>.D | 7.100 |
t1/div<1>.Q | t1/shdata<3>.D | 7.100 |
t1/div<1>.Q | t1/shdata<4>.D | 7.100 |
t1/div<1>.Q | t1/shdata<5>.D | 7.100 |
t1/div<1>.Q | t1/shdata<6>.D | 7.100 |
t1/div<1>.Q | t1/shdata<7>.D | 7.100 |
t1/div<1>.Q | t1/shdata<8>.D | 7.100 |
t1/div<1>.Q | t1/shdata<9>.D | 7.100 |
t1/shdata<1>.Q | SEND.D | 7.100 |
t1/shdata<1>.Q | t1/shdata<1>.D | 7.100 |
t1/shdata<2>.Q | t1/shdata<1>.D | 7.100 |
t1/shdata<2>.Q | t1/shdata<2>.D | 7.100 |
t1/shdata<3>.Q | t1/shdata<2>.D | 7.100 |
t1/shdata<3>.Q | t1/shdata<3>.D | 7.100 |
t1/shdata<4>.Q | t1/shdata<3>.D | 7.100 |
t1/shdata<4>.Q | t1/shdata<4>.D | 7.100 |
t1/shdata<5>.Q | t1/shdata<4>.D | 7.100 |
t1/shdata<5>.Q | t1/shdata<5>.D | 7.100 |
t1/shdata<6>.Q | t1/shdata<5>.D | 7.100 |
t1/shdata<6>.Q | t1/shdata<6>.D | 7.100 |
t1/shdata<7>.Q | t1/shdata<6>.D | 7.100 |
t1/shdata<7>.Q | t1/shdata<7>.D | 7.100 |
t1/shdata<8>.Q | t1/shdata<7>.D | 7.100 |
t1/shdata<8>.Q | t1/shdata<8>.D | 7.100 |
t1/shdata<9>.Q | t1/shdata<8>.D | 7.100 |
t1/shdata<9>.Q | t1/shdata<9>.D | 7.100 |
tr_inproc.Q | SEND.D | 7.100 |
tr_inproc.Q | t1/bitsz<0>.D | 7.100 |
tr_inproc.Q | t1/bitsz<1>.D | 7.100 |
tr_inproc.Q | t1/bitsz<2>.D | 7.100 |
tr_inproc.Q | t1/bitsz<3>.D | 7.100 |
tr_inproc.Q | t1/shdata<1>.D | 7.100 |
tr_inproc.Q | t1/shdata<2>.D | 7.100 |
tr_inproc.Q | t1/shdata<3>.D | 7.100 |
tr_inproc.Q | t1/shdata<4>.D | 7.100 |
tr_inproc.Q | t1/shdata<5>.D | 7.100 |
tr_inproc.Q | t1/shdata<6>.D | 7.100 |
tr_inproc.Q | t1/shdata<7>.D | 7.100 |
tr_inproc.Q | t1/shdata<8>.D | 7.100 |
tr_inproc.Q | t1/shdata<9>.D | 7.100 |
trmt.Q | SEND.D | 7.100 |
trmt.Q | t1/bitsz<0>.D | 7.100 |
trmt.Q | t1/bitsz<1>.D | 7.100 |
trmt.Q | t1/bitsz<2>.D | 7.100 |
trmt.Q | t1/bitsz<3>.D | 7.100 |
trmt.Q | t1/shdata<1>.D | 7.100 |
trmt.Q | t1/shdata<2>.D | 7.100 |
trmt.Q | t1/shdata<3>.D | 7.100 |
trmt.Q | t1/shdata<4>.D | 7.100 |
trmt.Q | t1/shdata<5>.D | 7.100 |
trmt.Q | t1/shdata<6>.D | 7.100 |
trmt.Q | t1/shdata<7>.D | 7.100 |
trmt.Q | t1/shdata<8>.D | 7.100 |
trmt.Q | t1/shdata<9>.D | 7.100 |
trmt.Q | tr_inproc.D | 7.100 |
r1/csample<0>.Q | bus1<0>.CE | 6.900 |
r1/csample<0>.Q | bus1<1>.CE | 6.900 |
r1/csample<0>.Q | bus1<2>.CE | 6.900 |
r1/csample<0>.Q | bus1<3>.CE | 6.900 |
r1/csample<0>.Q | bus1<4>.CE | 6.900 |
r1/csample<0>.Q | bus1<5>.CE | 6.900 |
r1/csample<0>.Q | bus1<6>.CE | 6.900 |
r1/csample<0>.Q | bus1<7>.CE | 6.900 |
r1/csample<0>.Q | r1/data<9>.CE | 6.900 |
r1/csample<1>.Q | bus1<0>.CE | 6.900 |
r1/csample<1>.Q | bus1<1>.CE | 6.900 |
r1/csample<1>.Q | bus1<2>.CE | 6.900 |
r1/csample<1>.Q | bus1<3>.CE | 6.900 |
r1/csample<1>.Q | bus1<4>.CE | 6.900 |
r1/csample<1>.Q | bus1<5>.CE | 6.900 |
r1/csample<1>.Q | bus1<6>.CE | 6.900 |
r1/csample<1>.Q | bus1<7>.CE | 6.900 |
r1/csample<1>.Q | r1/data<9>.CE | 6.900 |
r1/startb.Q | OUT<0>.CE | 6.900 |
r1/startb.Q | bus1<0>.CE | 6.900 |
r1/startb.Q | bus1<1>.CE | 6.900 |
r1/startb.Q | bus1<2>.CE | 6.900 |
r1/startb.Q | bus1<3>.CE | 6.900 |
r1/startb.Q | bus1<4>.CE | 6.900 |
r1/startb.Q | bus1<5>.CE | 6.900 |
r1/startb.Q | bus1<6>.CE | 6.900 |
r1/startb.Q | bus1<7>.CE | 6.900 |
r1/startb.Q | r1/data<9>.CE | 6.900 |
bus1<2>.Q | OUT<2>.D | 6.600 |
bus1<3>.Q | OUT<3>.D | 6.600 |
bus1<4>.Q | OUT<4>.D | 6.600 |
bus1<6>.Q | OUT<6>.D | 6.600 |
bus1<7>.Q | OUT<7>.D | 6.600 |
postsc<0>.Q | postsc<10>.D | 6.600 |
postsc<0>.Q | postsc<11>.D | 6.600 |
postsc<0>.Q | postsc<12>.D | 6.600 |
postsc<0>.Q | postsc<13>.D | 6.600 |
postsc<0>.Q | postsc<14>.D | 6.600 |
postsc<0>.Q | postsc<15>.D | 6.600 |
postsc<0>.Q | postsc<1>.D | 6.600 |
postsc<0>.Q | postsc<2>.D | 6.600 |
postsc<0>.Q | postsc<3>.D | 6.600 |
postsc<0>.Q | postsc<4>.D | 6.600 |
postsc<0>.Q | postsc<5>.D | 6.600 |
postsc<0>.Q | postsc<6>.D | 6.600 |
postsc<0>.Q | postsc<7>.D | 6.600 |
postsc<0>.Q | postsc<8>.D | 6.600 |
postsc<0>.Q | postsc<9>.D | 6.600 |
postsc<0>.Q | trmt.D | 6.600 |
postsc<10>.Q | postsc<11>.D | 6.600 |
postsc<10>.Q | postsc<12>.D | 6.600 |
postsc<10>.Q | postsc<13>.D | 6.600 |
postsc<10>.Q | postsc<14>.D | 6.600 |
postsc<10>.Q | postsc<15>.D | 6.600 |
postsc<10>.Q | trmt.D | 6.600 |
postsc<11>.Q | postsc<12>.D | 6.600 |
postsc<11>.Q | postsc<13>.D | 6.600 |
postsc<11>.Q | postsc<14>.D | 6.600 |
postsc<11>.Q | postsc<15>.D | 6.600 |
postsc<11>.Q | trmt.D | 6.600 |
postsc<12>.Q | postsc<13>.D | 6.600 |
postsc<12>.Q | postsc<14>.D | 6.600 |
postsc<12>.Q | postsc<15>.D | 6.600 |
postsc<12>.Q | trmt.D | 6.600 |
postsc<13>.Q | postsc<14>.D | 6.600 |
postsc<13>.Q | postsc<15>.D | 6.600 |
postsc<13>.Q | trmt.D | 6.600 |
postsc<14>.Q | postsc<15>.D | 6.600 |
postsc<14>.Q | trmt.D | 6.600 |
postsc<15>.Q | trmt.D | 6.600 |
postsc<1>.Q | postsc<10>.D | 6.600 |
postsc<1>.Q | postsc<11>.D | 6.600 |
postsc<1>.Q | postsc<12>.D | 6.600 |
postsc<1>.Q | postsc<13>.D | 6.600 |
postsc<1>.Q | postsc<14>.D | 6.600 |
postsc<1>.Q | postsc<15>.D | 6.600 |
postsc<1>.Q | postsc<2>.D | 6.600 |
postsc<1>.Q | postsc<3>.D | 6.600 |
postsc<1>.Q | postsc<4>.D | 6.600 |
postsc<1>.Q | postsc<5>.D | 6.600 |
postsc<1>.Q | postsc<6>.D | 6.600 |
postsc<1>.Q | postsc<7>.D | 6.600 |
postsc<1>.Q | postsc<8>.D | 6.600 |
postsc<1>.Q | postsc<9>.D | 6.600 |
postsc<1>.Q | trmt.D | 6.600 |
postsc<2>.Q | postsc<10>.D | 6.600 |
postsc<2>.Q | postsc<11>.D | 6.600 |
postsc<2>.Q | postsc<12>.D | 6.600 |
postsc<2>.Q | postsc<13>.D | 6.600 |
postsc<2>.Q | postsc<14>.D | 6.600 |
postsc<2>.Q | postsc<15>.D | 6.600 |
postsc<2>.Q | postsc<3>.D | 6.600 |
postsc<2>.Q | postsc<4>.D | 6.600 |
postsc<2>.Q | postsc<5>.D | 6.600 |
postsc<2>.Q | postsc<6>.D | 6.600 |
postsc<2>.Q | postsc<7>.D | 6.600 |
postsc<2>.Q | postsc<8>.D | 6.600 |
postsc<2>.Q | postsc<9>.D | 6.600 |
postsc<2>.Q | trmt.D | 6.600 |
postsc<3>.Q | postsc<10>.D | 6.600 |
postsc<3>.Q | postsc<11>.D | 6.600 |
postsc<3>.Q | postsc<12>.D | 6.600 |
postsc<3>.Q | postsc<13>.D | 6.600 |
postsc<3>.Q | postsc<14>.D | 6.600 |
postsc<3>.Q | postsc<15>.D | 6.600 |
postsc<3>.Q | postsc<4>.D | 6.600 |
postsc<3>.Q | postsc<5>.D | 6.600 |
postsc<3>.Q | postsc<6>.D | 6.600 |
postsc<3>.Q | postsc<7>.D | 6.600 |
postsc<3>.Q | postsc<8>.D | 6.600 |
postsc<3>.Q | postsc<9>.D | 6.600 |
postsc<3>.Q | trmt.D | 6.600 |
postsc<4>.Q | postsc<10>.D | 6.600 |
postsc<4>.Q | postsc<11>.D | 6.600 |
postsc<4>.Q | postsc<12>.D | 6.600 |
postsc<4>.Q | postsc<13>.D | 6.600 |
postsc<4>.Q | postsc<14>.D | 6.600 |
postsc<4>.Q | postsc<15>.D | 6.600 |
postsc<4>.Q | postsc<5>.D | 6.600 |
postsc<4>.Q | postsc<6>.D | 6.600 |
postsc<4>.Q | postsc<7>.D | 6.600 |
postsc<4>.Q | postsc<8>.D | 6.600 |
postsc<4>.Q | postsc<9>.D | 6.600 |
postsc<4>.Q | trmt.D | 6.600 |
postsc<5>.Q | postsc<10>.D | 6.600 |
postsc<5>.Q | postsc<11>.D | 6.600 |
postsc<5>.Q | postsc<12>.D | 6.600 |
postsc<5>.Q | postsc<13>.D | 6.600 |
postsc<5>.Q | postsc<14>.D | 6.600 |
postsc<5>.Q | postsc<15>.D | 6.600 |
postsc<5>.Q | postsc<6>.D | 6.600 |
postsc<5>.Q | postsc<7>.D | 6.600 |
postsc<5>.Q | postsc<8>.D | 6.600 |
postsc<5>.Q | postsc<9>.D | 6.600 |
postsc<5>.Q | trmt.D | 6.600 |
postsc<6>.Q | postsc<10>.D | 6.600 |
postsc<6>.Q | postsc<11>.D | 6.600 |
postsc<6>.Q | postsc<12>.D | 6.600 |
postsc<6>.Q | postsc<13>.D | 6.600 |
postsc<6>.Q | postsc<14>.D | 6.600 |
postsc<6>.Q | postsc<15>.D | 6.600 |
postsc<6>.Q | postsc<7>.D | 6.600 |
postsc<6>.Q | postsc<8>.D | 6.600 |
postsc<6>.Q | postsc<9>.D | 6.600 |
postsc<6>.Q | trmt.D | 6.600 |
postsc<7>.Q | postsc<10>.D | 6.600 |
postsc<7>.Q | postsc<11>.D | 6.600 |
postsc<7>.Q | postsc<12>.D | 6.600 |
postsc<7>.Q | postsc<13>.D | 6.600 |
postsc<7>.Q | postsc<14>.D | 6.600 |
postsc<7>.Q | postsc<15>.D | 6.600 |
postsc<7>.Q | postsc<8>.D | 6.600 |
postsc<7>.Q | postsc<9>.D | 6.600 |
postsc<7>.Q | trmt.D | 6.600 |
postsc<8>.Q | postsc<10>.D | 6.600 |
postsc<8>.Q | postsc<11>.D | 6.600 |
postsc<8>.Q | postsc<12>.D | 6.600 |
postsc<8>.Q | postsc<13>.D | 6.600 |
postsc<8>.Q | postsc<14>.D | 6.600 |
postsc<8>.Q | postsc<15>.D | 6.600 |
postsc<8>.Q | postsc<9>.D | 6.600 |
postsc<8>.Q | trmt.D | 6.600 |
postsc<9>.Q | postsc<10>.D | 6.600 |
postsc<9>.Q | postsc<11>.D | 6.600 |
postsc<9>.Q | postsc<12>.D | 6.600 |
postsc<9>.Q | postsc<13>.D | 6.600 |
postsc<9>.Q | postsc<14>.D | 6.600 |
postsc<9>.Q | postsc<15>.D | 6.600 |
postsc<9>.Q | trmt.D | 6.600 |
r1/csample<0>.Q | r1/csample<0>.D | 6.600 |
r1/csample<0>.Q | r1/csample<1>.D | 6.600 |
r1/csample<1>.Q | r1/csample<0>.D | 6.600 |
r1/csample<1>.Q | r1/csample<1>.D | 6.600 |
r1/startb.Q | r1/csample<0>.D | 6.600 |
r1/startb.Q | r1/csample<1>.D | 6.600 |
t1/div<0>.Q | t1/div<0>.D | 6.600 |
t1/div<0>.Q | t1/div<1>.D | 6.600 |
t1/div<1>.Q | t1/div<0>.D | 6.600 |
t1/div<1>.Q | t1/div<1>.D | 6.600 |
tr_inproc.Q | trmt.D | 6.600 |
trmt.Q | t1/div<0>.D | 6.600 |
trmt.Q | t1/div<1>.D | 6.600 |
Source Pad | Destination Pad | Delay |
---|