Timing Report

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Design Name serial
Device, Speed (SpeedFile Version) XC2C256, -7 (14.0 Advance Product Specification)
Date Created Wed May 16 15:22:21 2007
Created By Timing Report Generator: version I.31
Copyright Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.

Summary

Performance Summary
Min. Clock Period 7.100 ns.
Max. Clock Frequency (fSYSTEM) 140.845 MHz.
Limited by Cycle Time for CLKOUT_MC.Q
Clock to Setup (tCYC) 7.100 ns.
Setup to Clock at the Pad (tSU) 1.600 ns.
Clock Pad to Output Pad Delay (tCO) 13.400 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS_CLK 0.0 6.6 15 15


Constraint: TS_CLK

Description: PERIOD:CLK:.nS:HIGH:20.000nS
Path Requirement (ns) Delay (ns) Slack (ns)
p1/prescale<0>.Q to CLKOUT.D 0.000 6.600 -6.600
p1/prescale<0>.Q to p1/prescale<1>.D 0.000 6.600 -6.600
p1/prescale<0>.Q to p1/prescale<2>.D 0.000 6.600 -6.600



Number of constraints not met: 1

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
CLKOUT_MC.Q 140.845 Limited by Cycle Time for CLKOUT_MC.Q
CLK 151.515 Limited by Cycle Time for CLK

Setup/Hold Times for Clocks

Setup/Hold Times for Clock CLKOUT.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
REC 1.600 0.000


Clock to Pad Timing

Clock CLK to Pad
Destination Pad Clock (edge) to Pad
OUT<0> 13.400
OUT<1> 13.400
OUT<2> 13.400
OUT<3> 13.400
OUT<4> 13.400
OUT<5> 13.400
OUT<6> 13.400
OUT<7> 13.400
ST 13.400
CLKOUT 8.300


Clock to Setup Times for Clocks

Clock to Setup for clock CLKOUT.Q
Source Destination Delay
OUT<1>.Q OUT<0>.D 7.100
OUT<2>.Q OUT<1>.D 7.100
OUT<3>.Q OUT<2>.D 7.100
OUT<4>.Q OUT<3>.D 7.100
OUT<5>.Q OUT<4>.D 7.100
OUT<6>.Q OUT<5>.D 7.100
OUT<7>.Q OUT<6>.D 7.100
ST.Q ST.D 7.100
ST.Q r1/cbit<0>.D 7.100
ST.Q r1/cbit<1>.D 7.100
ST.Q r1/cbit<2>.D 7.100
ST.Q r1/cbit<3>.D 7.100
ST.Q r1/data<8>.D 7.100
r1/cbit<0>.Q ST.D 7.100
r1/cbit<0>.Q r1/cbit<0>.D 7.100
r1/cbit<0>.Q r1/cbit<1>.D 7.100
r1/cbit<0>.Q r1/cbit<2>.D 7.100
r1/cbit<0>.Q r1/cbit<3>.D 7.100
r1/cbit<1>.Q ST.D 7.100
r1/cbit<1>.Q r1/cbit<0>.D 7.100
r1/cbit<1>.Q r1/cbit<1>.D 7.100
r1/cbit<1>.Q r1/cbit<2>.D 7.100
r1/cbit<1>.Q r1/cbit<3>.D 7.100
r1/cbit<2>.Q ST.D 7.100
r1/cbit<2>.Q r1/cbit<0>.D 7.100
r1/cbit<2>.Q r1/cbit<1>.D 7.100
r1/cbit<2>.Q r1/cbit<2>.D 7.100
r1/cbit<2>.Q r1/cbit<3>.D 7.100
r1/cbit<3>.Q ST.D 7.100
r1/cbit<3>.Q r1/cbit<0>.D 7.100
r1/cbit<3>.Q r1/cbit<1>.D 7.100
r1/cbit<3>.Q r1/cbit<3>.D 7.100
r1/csample<0>.Q ST.D 7.100
r1/csample<0>.Q r1/cbit<0>.D 7.100
r1/csample<0>.Q r1/cbit<1>.D 7.100
r1/csample<0>.Q r1/cbit<2>.D 7.100
r1/csample<0>.Q r1/cbit<3>.D 7.100
r1/csample<0>.Q r1/data<8>.D 7.100
r1/csample<1>.Q ST.D 7.100
r1/csample<1>.Q r1/cbit<0>.D 7.100
r1/csample<1>.Q r1/cbit<1>.D 7.100
r1/csample<1>.Q r1/cbit<2>.D 7.100
r1/csample<1>.Q r1/cbit<3>.D 7.100
r1/csample<1>.Q r1/data<8>.D 7.100
r1/data<8>.Q OUT<7>.D 7.100
r1/data<8>.Q r1/data<8>.D 7.100
r1/data<9>.Q r1/data<8>.D 7.100
ST.Q OUT<0>.CE 6.900
ST.Q OUT<1>.CE 6.900
ST.Q OUT<2>.CE 6.900
ST.Q OUT<3>.CE 6.900
ST.Q OUT<4>.CE 6.900
ST.Q OUT<5>.CE 6.900
ST.Q OUT<6>.CE 6.900
ST.Q OUT<7>.CE 6.900
ST.Q r1/data<9>.CE 6.900
r1/csample<0>.Q OUT<0>.CE 6.900
r1/csample<0>.Q OUT<1>.CE 6.900
r1/csample<0>.Q OUT<2>.CE 6.900
r1/csample<0>.Q OUT<3>.CE 6.900
r1/csample<0>.Q OUT<4>.CE 6.900
r1/csample<0>.Q OUT<5>.CE 6.900
r1/csample<0>.Q OUT<6>.CE 6.900
r1/csample<0>.Q OUT<7>.CE 6.900
r1/csample<0>.Q r1/data<9>.CE 6.900
r1/csample<1>.Q OUT<0>.CE 6.900
r1/csample<1>.Q OUT<1>.CE 6.900
r1/csample<1>.Q OUT<2>.CE 6.900
r1/csample<1>.Q OUT<3>.CE 6.900
r1/csample<1>.Q OUT<4>.CE 6.900
r1/csample<1>.Q OUT<5>.CE 6.900
r1/csample<1>.Q OUT<6>.CE 6.900
r1/csample<1>.Q OUT<7>.CE 6.900
r1/csample<1>.Q r1/data<9>.CE 6.900
ST.Q r1/csample<0>.D 6.600
ST.Q r1/csample<1>.D 6.600
r1/csample<0>.Q r1/csample<0>.D 6.600
r1/csample<0>.Q r1/csample<1>.D 6.600
r1/csample<1>.Q r1/csample<0>.D 6.600
r1/csample<1>.Q r1/csample<1>.D 6.600

Clock to Setup for clock CLK
Source Destination Delay
p1/prescale<0>.Q CLKOUT.D 6.600
p1/prescale<0>.Q p1/prescale<1>.D 6.600
p1/prescale<0>.Q p1/prescale<2>.D 6.600
p1/prescale<0>.Q p1/prescale<3>.D 6.600
p1/prescale<0>.Q p1/prescale<4>.D 6.600
p1/prescale<1>.Q CLKOUT.D 6.600
p1/prescale<1>.Q p1/prescale<2>.D 6.600
p1/prescale<1>.Q p1/prescale<3>.D 6.600
p1/prescale<1>.Q p1/prescale<4>.D 6.600
p1/prescale<2>.Q CLKOUT.D 6.600
p1/prescale<2>.Q p1/prescale<3>.D 6.600
p1/prescale<2>.Q p1/prescale<4>.D 6.600
p1/prescale<3>.Q CLKOUT.D 6.600
p1/prescale<3>.Q p1/prescale<4>.D 6.600
p1/prescale<4>.Q CLKOUT.D 6.600


Pad to Pad List

Source Pad Destination Pad Delay



Number of paths analyzed: 15
Number of Timing errors: 15
Analysis Completed: Wed May 16 15:22:21 2007