********** Mapped Logic ********** |
FDCPE_CLKOUT: FDCPE port map (CLKOUT,CLKOUT_D,CLK,'0','0','1');
CLKOUT_D <= (p1/prescale(0) AND p1/prescale(1) AND p1/prescale(2) AND p1/prescale(3) AND p1/prescale(4)); |
DIR1 <= NOT ('0'); |
EN1 <= '0'; |
FDCPE_OUT0: FDCPE port map (OUT(0),OUT(1),CLKOUT,'0','0',OUT_CE(0));
OUT_CE(0) <= (ST AND NOT r1/csample(0) AND r1/csample(1)); |
FDCPE_OUT1: FDCPE port map (OUT(1),OUT(2),CLKOUT,'0','0',OUT_CE(1));
OUT_CE(1) <= (ST AND NOT r1/csample(0) AND r1/csample(1)); |
FDCPE_OUT2: FDCPE port map (OUT(2),OUT(3),CLKOUT,'0','0',OUT_CE(2));
OUT_CE(2) <= (ST AND NOT r1/csample(0) AND r1/csample(1)); |
FDCPE_OUT3: FDCPE port map (OUT(3),OUT(4),CLKOUT,'0','0',OUT_CE(3));
OUT_CE(3) <= (ST AND NOT r1/csample(0) AND r1/csample(1)); |
FDCPE_OUT4: FDCPE port map (OUT(4),OUT(5),CLKOUT,'0','0',OUT_CE(4));
OUT_CE(4) <= (ST AND NOT r1/csample(0) AND r1/csample(1)); |
FDCPE_OUT5: FDCPE port map (OUT(5),OUT(6),CLKOUT,'0','0',OUT_CE(5));
OUT_CE(5) <= (ST AND NOT r1/csample(0) AND r1/csample(1)); |
FDCPE_OUT6: FDCPE port map (OUT(6),OUT(7),CLKOUT,'0','0',OUT_CE(6));
OUT_CE(6) <= (ST AND NOT r1/csample(0) AND r1/csample(1)); |
FDCPE_OUT7: FDCPE port map (OUT(7),r1/data(8),CLKOUT,'0','0',OUT_CE(7));
OUT_CE(7) <= (ST AND NOT r1/csample(0) AND r1/csample(1)); |
SEND <= NOT ('0'); |
FDCPE_ST: FDCPE port map (ST,ST_D,CLKOUT,'0','0','1');
ST_D <= NOT (((NOT ST AND REC) OR (ST AND NOT r1/cbit(0) AND r1/cbit(1) AND NOT r1/csample(0) AND NOT r1/csample(1) AND NOT r1/cbit(2) AND r1/cbit(3)))); |
FTCPE_p1/prescale0: FTCPE port map (p1/prescale(0),'0',CLK,'0','0','1'); |
FTCPE_p1/prescale1: FTCPE port map (p1/prescale(1),p1/prescale(0),CLK,'0','0','1'); |
FTCPE_p1/prescale2: FTCPE port map (p1/prescale(2),p1/prescale_T(2),CLK,'0','0','1');
p1/prescale_T(2) <= (p1/prescale(0) AND p1/prescale(1)); |
FTCPE_p1/prescale3: FTCPE port map (p1/prescale(3),p1/prescale_T(3),CLK,'0','0','1');
p1/prescale_T(3) <= (p1/prescale(0) AND p1/prescale(1) AND p1/prescale(2)); |
FTCPE_p1/prescale4: FTCPE port map (p1/prescale(4),p1/prescale_T(4),CLK,'0','0','1');
p1/prescale_T(4) <= (p1/prescale(0) AND p1/prescale(1) AND p1/prescale(2) AND p1/prescale(3)); |
FTCPE_r1/cbit0: FTCPE port map (r1/cbit(0),r1/cbit_T(0),CLKOUT,'0','0','1');
r1/cbit_T(0) <= NOT (((ST AND r1/csample(0)) OR (ST AND r1/csample(1)) OR (NOT ST AND NOT r1/cbit(0)) OR (NOT r1/cbit(0) AND r1/cbit(1) AND NOT r1/cbit(2) AND r1/cbit(3)))); |
FTCPE_r1/cbit1: FTCPE port map (r1/cbit(1),r1/cbit_T(1),CLKOUT,'0','0','1');
r1/cbit_T(1) <= ((NOT ST AND r1/cbit(1)) OR (ST AND r1/cbit(0) AND NOT r1/csample(0) AND NOT r1/csample(1)) OR (r1/cbit(1) AND NOT r1/csample(0) AND NOT r1/csample(1) AND NOT r1/cbit(2) AND r1/cbit(3))); |
FTCPE_r1/cbit2: FTCPE port map (r1/cbit(2),r1/cbit_T(2),CLKOUT,'0','0','1');
r1/cbit_T(2) <= ((NOT ST AND r1/cbit(2)) OR (ST AND r1/cbit(0) AND r1/cbit(1) AND NOT r1/csample(0) AND NOT r1/csample(1))); |
FTCPE_r1/cbit3: FTCPE port map (r1/cbit(3),r1/cbit_T(3),CLKOUT,'0','0','1');
r1/cbit_T(3) <= ((NOT ST AND r1/cbit(3)) OR (ST AND r1/cbit(0) AND r1/cbit(1) AND NOT r1/csample(0) AND NOT r1/csample(1) AND r1/cbit(2)) OR (NOT r1/cbit(0) AND r1/cbit(1) AND NOT r1/csample(0) AND NOT r1/csample(1) AND NOT r1/cbit(2) AND r1/cbit(3))); |
FDCPE_r1/csample0: FDCPE port map (r1/csample(0),r1/csample_D(0),CLKOUT,'0','0','1');
r1/csample_D(0) <= (ST AND NOT r1/csample(0) AND NOT r1/csample(1)); |
FDCPE_r1/csample1: FDCPE port map (r1/csample(1),r1/csample_D(1),CLKOUT,'0','0','1');
r1/csample_D(1) <= (ST AND r1/csample(0) AND NOT r1/csample(1)); |
FTCPE_r1/data8: FTCPE port map (r1/data(8),r1/data_T(8),CLKOUT,'0','0','1');
r1/data_T(8) <= ((r1/data(8) AND ST AND NOT r1/csample(0) AND r1/csample(1) AND NOT r1/data(9)) OR (NOT r1/data(8) AND ST AND NOT r1/csample(0) AND r1/csample(1) AND r1/data(9))); |
FDCPE_r1/data9: FDCPE port map (r1/data(9),REC,CLKOUT,'0','0',r1/data_CE(9));
r1/data_CE(9) <= (ST AND NOT r1/csample(0) AND NOT r1/csample(1)); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FDDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); FTDCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |