********** Mapped Logic ********** |
DIR1 <= NOT ('0'); |
EN1 <= '0'; |
FDCPE_Q10: FDCPE port map (Q1(0),Q1(7),line1,'0','0','1'); |
FDCPE_Q11: FDCPE port map (Q1(1),SEND,line1,'0','0','1'); |
FDCPE_Q12: FDCPE port map (Q1(2),Q1(1),line1,'0','0','1'); |
FDCPE_Q13: FDCPE port map (Q1(3),Q1(2),line1,'0','0','1'); |
FDCPE_Q14: FDCPE port map (Q1(4),Q1(3),line1,'0','0','1'); |
FDCPE_Q15: FDCPE port map (Q1(5),Q1(4),line1,'0','0','1'); |
FDCPE_Q16: FDCPE port map (Q1(6),Q1(5),line1,'0','0','1'); |
FDCPE_Q17: FDCPE port map (Q1(7),Q1(6),line1,'0','0','1'); |
FDCPE_SEND: FDCPE port map (SEND,Q1(7),line1,'0','0','1'); |
FDCPE_line1: FDCPE port map (line1,line1_D,CLK,'0','0','1');
line1_D <= (prescale(0) AND prescale(10) AND prescale(1) AND prescale(2) AND prescale(3) AND prescale(4) AND prescale(5) AND prescale(6) AND prescale(7) AND prescale(8) AND prescale(9) AND prescale(11) AND prescale(12) AND prescale(13) AND prescale(14) AND prescale(15) AND prescale(16) AND prescale(17) AND prescale(18) AND prescale(19)); |
FDCPE_prescale0: FDCPE port map (prescale(0),REC,CLK,'0','0','1'); |
FTCPE_prescale1: FTCPE port map (prescale(1),prescale_T(1),CLK,'0','0','1');
prescale_T(1) <= (prescale(0) AND REC); |
FTCPE_prescale2: FTCPE port map (prescale(2),prescale_T(2),CLK,'0','0','1');
prescale_T(2) <= (prescale(0) AND REC AND prescale(1)); |
FTCPE_prescale3: FTCPE port map (prescale(3),prescale_T(3),CLK,'0','0','1');
prescale_T(3) <= (prescale(0) AND REC AND prescale(1) AND prescale(2)); |
FTCPE_prescale4: FTCPE port map (prescale(4),prescale_T(4),CLK,'0','0','1');
prescale_T(4) <= (prescale(0) AND REC AND prescale(1) AND prescale(2) AND prescale(3)); |
FTCPE_prescale5: FTCPE port map (prescale(5),prescale_T(5),CLK,'0','0','1');
prescale_T(5) <= (prescale(0) AND REC AND prescale(1) AND prescale(2) AND prescale(3) AND prescale(4)); |
FTCPE_prescale6: FTCPE port map (prescale(6),prescale_T(6),CLK,'0','0','1');
prescale_T(6) <= (prescale(0) AND REC AND prescale(1) AND prescale(2) AND prescale(3) AND prescale(4) AND prescale(5)); |
FTCPE_prescale7: FTCPE port map (prescale(7),prescale_T(7),CLK,'0','0','1');
prescale_T(7) <= (prescale(0) AND REC AND prescale(1) AND prescale(2) AND prescale(3) AND prescale(4) AND prescale(5) AND prescale(6)); |
FTCPE_prescale8: FTCPE port map (prescale(8),prescale_T(8),CLK,'0','0','1');
prescale_T(8) <= (prescale(0) AND REC AND prescale(1) AND prescale(2) AND prescale(3) AND prescale(4) AND prescale(5) AND prescale(6) AND prescale(7)); |
FTCPE_prescale9: FTCPE port map (prescale(9),prescale_T(9),CLK,'0','0','1');
prescale_T(9) <= (prescale(0) AND REC AND prescale(1) AND prescale(2) AND prescale(3) AND prescale(4) AND prescale(5) AND prescale(6) AND prescale(7) AND prescale(8)); |
FTCPE_prescale10: FTCPE port map (prescale(10),prescale_T(10),CLK,'0','0','1');
prescale_T(10) <= (prescale(0) AND REC AND prescale(1) AND prescale(2) AND prescale(3) AND prescale(4) AND prescale(5) AND prescale(6) AND prescale(7) AND prescale(8) AND prescale(9)); |
FTCPE_prescale11: FTCPE port map (prescale(11),prescale_T(11),CLK,'0','0','1');
prescale_T(11) <= (prescale(0) AND prescale(10) AND REC AND prescale(1) AND prescale(2) AND prescale(3) AND prescale(4) AND prescale(5) AND prescale(6) AND prescale(7) AND prescale(8) AND prescale(9)); |
FTCPE_prescale12: FTCPE port map (prescale(12),prescale_T(12),CLK,'0','0','1');
prescale_T(12) <= (prescale(0) AND prescale(10) AND REC AND prescale(1) AND prescale(2) AND prescale(3) AND prescale(4) AND prescale(5) AND prescale(6) AND prescale(7) AND prescale(8) AND prescale(9) AND prescale(11)); |
FTCPE_prescale13: FTCPE port map (prescale(13),prescale_T(13),CLK,'0','0','1');
prescale_T(13) <= (prescale(0) AND prescale(10) AND REC AND prescale(1) AND prescale(2) AND prescale(3) AND prescale(4) AND prescale(5) AND prescale(6) AND prescale(7) AND prescale(8) AND prescale(9) AND prescale(11) AND prescale(12)); |
FTCPE_prescale14: FTCPE port map (prescale(14),prescale_T(14),CLK,'0','0','1');
prescale_T(14) <= (prescale(0) AND prescale(10) AND REC AND prescale(1) AND prescale(2) AND prescale(3) AND prescale(4) AND prescale(5) AND prescale(6) AND prescale(7) AND prescale(8) AND prescale(9) AND prescale(11) AND prescale(12) AND prescale(13)); |
FTCPE_prescale15: FTCPE port map (prescale(15),prescale_T(15),CLK,'0','0','1');
prescale_T(15) <= (prescale(0) AND prescale(10) AND REC AND prescale(1) AND prescale(2) AND prescale(3) AND prescale(4) AND prescale(5) AND prescale(6) AND prescale(7) AND prescale(8) AND prescale(9) AND prescale(11) AND prescale(12) AND prescale(13) AND prescale(14)); |
FTCPE_prescale16: FTCPE port map (prescale(16),prescale_T(16),CLK,'0','0','1');
prescale_T(16) <= (prescale(0) AND prescale(10) AND REC AND prescale(1) AND prescale(2) AND prescale(3) AND prescale(4) AND prescale(5) AND prescale(6) AND prescale(7) AND prescale(8) AND prescale(9) AND prescale(11) AND prescale(12) AND prescale(13) AND prescale(14) AND prescale(15)); |
FTCPE_prescale17: FTCPE port map (prescale(17),prescale_T(17),CLK,'0','0','1');
prescale_T(17) <= (prescale(0) AND prescale(10) AND REC AND prescale(1) AND prescale(2) AND prescale(3) AND prescale(4) AND prescale(5) AND prescale(6) AND prescale(7) AND prescale(8) AND prescale(9) AND prescale(11) AND prescale(12) AND prescale(13) AND prescale(14) AND prescale(15) AND prescale(16)); |
FTCPE_prescale18: FTCPE port map (prescale(18),prescale_T(18),CLK,'0','0','1');
prescale_T(18) <= (prescale(0) AND prescale(10) AND REC AND prescale(1) AND prescale(2) AND prescale(3) AND prescale(4) AND prescale(5) AND prescale(6) AND prescale(7) AND prescale(8) AND prescale(9) AND prescale(11) AND prescale(12) AND prescale(13) AND prescale(14) AND prescale(15) AND prescale(16) AND prescale(17)); |
FTCPE_prescale19: FTCPE port map (prescale(19),prescale_T(19),CLK,'0','0','1');
prescale_T(19) <= (prescale(0) AND prescale(10) AND REC AND prescale(1) AND prescale(2) AND prescale(3) AND prescale(4) AND prescale(5) AND prescale(6) AND prescale(7) AND prescale(8) AND prescale(9) AND prescale(11) AND prescale(12) AND prescale(13) AND prescale(14) AND prescale(15) AND prescale(16) AND prescale(17) AND prescale(18)); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FDDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); FTDCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |