OSCILLTEST1 Project Status
Project File: oscilltest1.ise Current State: Programming File Generated
Module Name: proba1
  • Errors:
No Errors
Target Device: xc3s500e-4fg320
  • Warnings:
4 Warnings
Product Version: ISE 8.2.03i
  • Updated:
V ápr. 12 18:36:21 2009
 
OSCILLTEST1 Partition Summary
No partition information was found.
 
Device Utilization Summary
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 31 9,312 1%  
Number of 4 input LUTs 1 9,312 1%  
Logic Distribution     
Number of occupied Slices 16 4,656 1%  
    Number of Slices containing only related logic 16 16 100%  
    Number of Slices containing unrelated logic 0 16 0%  
Total Number 4 input LUTs 31 9,312 1%  
Number used as logic 1      
Number used as a route-thru 30      
Number of bonded IOBs 11 232 4%  
Number of GCLKs 1 24 4%  
Total equivalent gate count for design 437      
Additional JTAG gate count for IOBs 528      
 
Performance Summary
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentK febr. 3 20:33:55 2009000
Translation ReportCurrentK febr. 3 20:37:08 2009000
Map ReportCurrentK febr. 3 20:37:20 2009003 Infos
Place and Route ReportCurrentK febr. 3 20:37:42 200902 Warnings1 Info
Static Timing ReportCurrentK febr. 3 20:37:50 200902 Warnings1 Info
Bitgen ReportCurrentK febr. 3 20:38:03 2009000
 
Secondary Reports
Report NameStatusGenerated
Xplorer Report