DDR_EXPERIMENT6 Project Status | |||
Project File: | ddr_experiment6.ise | Current State: | Programming File Generated |
Module Name: | ddr_top |
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No Errors |
Target Device: | xc3s500e-4fg320 |
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81 Warnings |
Product Version: | ISE 8.2.03i |
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H ápr. 13 13:48:42 2009 |
DDR_EXPERIMENT6 Partition Summary | |||
No partition information was found. |
Device Utilization Summary | ||||
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops | 141 | 9,312 | 1% | |
Number of 4 input LUTs | 298 | 9,312 | 3% | |
Logic Distribution | ||||
Number of occupied Slices | 190 | 4,656 | 4% | |
Number of Slices containing only related logic | 190 | 190 | 100% | |
Number of Slices containing unrelated logic | 0 | 190 | 0% | |
Total Number 4 input LUTs | 308 | 9,312 | 3% | |
Number used as logic | 298 | |||
Number used as a route-thru | 10 | |||
Number of bonded IOBs | 50 | 232 | 21% | |
IOB Flip Flops | 26 | |||
Number of GCLKs | 4 | 24 | 16% | |
Number of DCMs | 1 | 4 | 25% | |
Total equivalent gate count for design | 10,430 | |||
Additional JTAG gate count for IOBs | 2,400 |
Performance Summary | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
Timing Constraints: | All Constraints Met |
Detailed Reports | |||||
Report Name | Status | Generated | Errors | Warnings | Infos |
Synthesis Report | Current | V ápr. 12 21:58:06 2009 | 0 | 76 Warnings | 11 Infos |
Translation Report | Current | V ápr. 12 21:58:24 2009 | 0 | 0 | 0 |
Map Report | Current | V ápr. 12 21:58:36 2009 | 0 | 1 Warning | 3 Infos |
Place and Route Report | Current | V ápr. 12 21:59:05 2009 | 0 | 1 Warning | 2 Infos |
Static Timing Report | Current | V ápr. 12 21:59:13 2009 | 0 | 2 Warnings | 2 Infos |
Bitgen Report | Current | V ápr. 12 21:59:30 2009 | 0 | 1 Warning | 0 |
Secondary Reports | ||
Report Name | Status | Generated |
Xplorer Report |