DDR_EXPERIMENT6 Project Status
Project File: ddr_experiment6.ise Current State: Programming File Generated
Module Name: ddr_top
  • Errors:
No Errors
Target Device: xc3s500e-4fg320
  • Warnings:
81 Warnings
Product Version: ISE 8.2.03i
  • Updated:
H ápr. 13 13:48:42 2009
 
DDR_EXPERIMENT6 Partition Summary
No partition information was found.
 
Device Utilization Summary
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 141 9,312 1%  
Number of 4 input LUTs 298 9,312 3%  
Logic Distribution     
Number of occupied Slices 190 4,656 4%  
    Number of Slices containing only related logic 190 190 100%  
    Number of Slices containing unrelated logic 0 190 0%  
Total Number 4 input LUTs 308 9,312 3%  
Number used as logic 298      
Number used as a route-thru 10      
Number of bonded IOBs 50 232 21%  
    IOB Flip Flops 26      
Number of GCLKs 4 24 16%  
Number of DCMs 1 4 25%  
Total equivalent gate count for design 10,430      
Additional JTAG gate count for IOBs 2,400      
 
Performance Summary
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentV ápr. 12 21:58:06 2009076 Warnings11 Infos
Translation ReportCurrentV ápr. 12 21:58:24 2009000
Map ReportCurrentV ápr. 12 21:58:36 200901 Warning3 Infos
Place and Route ReportCurrentV ápr. 12 21:59:05 200901 Warning2 Infos
Static Timing ReportCurrentV ápr. 12 21:59:13 200902 Warnings2 Infos
Bitgen ReportCurrentV ápr. 12 21:59:30 200901 Warning0
 
Secondary Reports
Report NameStatusGenerated
Xplorer Report