OSCILLTEST1 Project Status | |||
Project File: | oscilltest1.ise | Current State: | Programming File Generated |
Module Name: | proba1 |
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No Errors |
Target Device: | xc3s500e-4fg320 |
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4 Warnings |
Product Version: | ISE 8.2.03i |
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V ápr. 12 18:36:21 2009 |
OSCILLTEST1 Partition Summary | |||
No partition information was found. |
Device Utilization Summary | ||||
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops | 31 | 9,312 | 1% | |
Number of 4 input LUTs | 1 | 9,312 | 1% | |
Logic Distribution | ||||
Number of occupied Slices | 16 | 4,656 | 1% | |
Number of Slices containing only related logic | 16 | 16 | 100% | |
Number of Slices containing unrelated logic | 0 | 16 | 0% | |
Total Number 4 input LUTs | 31 | 9,312 | 1% | |
Number used as logic | 1 | |||
Number used as a route-thru | 30 | |||
Number of bonded IOBs | 11 | 232 | 4% | |
Number of GCLKs | 1 | 24 | 4% | |
Total equivalent gate count for design | 437 | |||
Additional JTAG gate count for IOBs | 528 |
Performance Summary | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
Timing Constraints: | All Constraints Met |
Detailed Reports | |||||
Report Name | Status | Generated | Errors | Warnings | Infos |
Synthesis Report | Current | K febr. 3 20:33:55 2009 | 0 | 0 | 0 |
Translation Report | Current | K febr. 3 20:37:08 2009 | 0 | 0 | 0 |
Map Report | Current | K febr. 3 20:37:20 2009 | 0 | 0 | 3 Infos |
Place and Route Report | Current | K febr. 3 20:37:42 2009 | 0 | 2 Warnings | 1 Info |
Static Timing Report | Current | K febr. 3 20:37:50 2009 | 0 | 2 Warnings | 1 Info |
Bitgen Report | Current | K febr. 3 20:38:03 2009 | 0 | 0 | 0 |
Secondary Reports | ||
Report Name | Status | Generated |
Xplorer Report |